The focus in all the discussions up to now has been on DSM VLSI chip performance issues related to the physical layout. The areas of application have included Hard IP retargeting to take advantage of existing designs and the latest technologies, efficient worry-free, IP creation that follows design rules, postlayout performance optimization through layout manipulations and design for manufacturing yield improve¬ments (DfM). In this chapter, we will examine commercial tools that help in addressing these issues.

We have reviewed the potential for affecting various performance parameters in DSM VLSI chips by manipulating the layout. Since both yield and performance are directly related to layout at the most detailed level, the polygon level, we are seeking tools that allow the necessary analysis related to physical layout parameters and then manipulation of the physical layout on the polygon level.

So far in this book, we have talked about concepts without naming commercially available tools with which to perform the necessary layout modifications. As one would expect, only some of what is theoretically known to be possible in layout manipulation and optimization has actually been implemented in commercially available tools. Additionally, no information could be obtained for some tools known to exist or rumored to be on the horizon. Accordingly, they will not be discussed here. This leaves us with a somewhat limited but still useful set of commercially available tools to be discussed.

Certain layout geometries in pre-DSM VLSI designs have traditionally been viewed as critical to the performance of ICs. Processing technology has therefore been pressed to make those critical layout geometries as small as possible, and remarkable success has been achieved in a very short time. Guidelines for the most critical process parameters have been based on computer simulations using the best known models for these circuits. At the heart of these models are active devices such as transistors. An enormous selection of models and corresponding software have been developed and are at the designer's disposal.

Lately, because of DSM effects in designs, the “ballgame” has changed dramatically due to the significant contribution of interconnects in determining the performance of designs fabricated in DSM processes.

Because of these relatively recent developments, an appreciation of the dominant effects determining the performance of DSM designs is rather limited and, therefore, the corresponding software to design and properly optimize these designs is also largely unavailable. This is a bit surprising since every year for the past years, an entire day has been dedicated to the subject of DSM layout optimization presented by the main contributor [3] of new insights at DAC, and extensive materials have been published over the past ten years suggesting algorithms containing the latest understanding of the main factors determining the performance parameters of DSM VLSI designs.

Is anybody out there in the commercial world listening!?

To reiterate, the dominant concerns in the VLSI chip industry over the last years have been:

  1. A conflict between the enormous investments in engineering resources and time required to come out with state-of-the-art VLSI chips and a shortening market window, jeopardizing a guaranteed return on investment.
  2. Accelerated time-to-market requirements.
  3. A growing discrepancy between the rate of progress in processing technology and the speed of design of new chips that benefit from it.
  4. An inability to design DSM VLSI chips to meet performance expectations without extensive rework. Often, a major redesign is even required.

One of the problems with these requirements is that their priorities shift constantly with time. Time-to-market is probably the most constant “squeaky wheel”. Whatever the crisis “du jour”, we will now discuss some available solutions regardless of whatever the priorities may be at the moment.


The postlayout optimization process may require any one, any combination of, or all of the following three steps, depending on the task to be performed.

The three steps are:

  1. The first step is an analysis of the nature of the problem. When performance problems arise or when increased performance is desired for whatever reason, an analysis is required to determine the problem. It may be a timing problem, an excessive power consumption problem, a yield problem, or another, more recent hot analysis issue such as problems with signal integrity.
  2. The second step is to determine what and how much in the layout needs to be changed. It is this second step that tells “compaction” which polygons to move and how much.
  3. The third step is the actual layout modification. Once the desired changes in the layout dimensions are known, these changes need to be implemented. This step is performed by means of “compaction” (an enlargement or reduction in layout dimensions).

In Chapter 3, we discussed some of the research results showing that, though they may be good starting points, neither an optimization of transistor geometries nor manipulations of interconnect geometries alone will lead to the best possible performance. A key realization gained from this research is that simultaneous optimization of interconnects and transistors driving them results in the greatest improvements with respect to speed, power dissipation and even layout density. Thus, based on the rather Warding results particularly with respect to the magnitude of these effects, we should expect some newer commercial tools that take into account both transistors and interconnects working together to come along in the near future.

Another key focus for layout manipulation is to improve manufacturing yield, preferably without sacrificing performance or chip size. We have already suggested in Chapters 3 and 5 that not all layout dimensions need to be the minimal layout dimensions allowed by the corresponding process. The trick is to relax the layout rules where no or little performance is sacrificed while significant yield improvements can be achieved. Such efforts will require close cooperation between processing and design engineers and the availability of good layout optimization analysis software.

This raises the following obvious and immediate question:
What tools are available to make the desired changes and what tools are available to efficiently analyze the required modifications?

We already have answered the first part of the question. The available compaction tools are exactly what we need to make the appropriate layout changes. All we need now is a few names of commercially available tools.

The second part of the question can not be answered as easily. With the main focus of the VLSI chip design community on synthesis, there is still only limited emphasis on layout optimization tools. The commercial tools currently available are limited to a traditional approach to layout optimization. The traditional approach is and has been to optimize the layout geometry of the active devices, the transistors. This was fine for pre-DSM processes, but the tools are only a starting point for DSM VLSI chips. Nevertheless, they are still useful and we will discuss them in this chapter.

As mentioned earlier, extensive work is being performed at the university level and very promising results have been published and algorithms found. Thus, even though many useful algorithms for optimization of DSM VLSI layouts have been published [3], they have not been “picked up” by the industry. At this point in time, these university level results are the only concrete results we can report that deal with physical layout optimization the way it should be done.

The main challenge in layout optimization seems to be that today only a handful of people in the industry believe or are aware of the possibility of significantly improving the performance of a chip through back-end, layout manipulation. To be fair, it is indeed almost counterintuitive to expect improvements larger than around 5 to 10% at that point in the design flow. However, one would think that if such improvements would save a chip that would otherwise have to be significantly redesigned, even 5% should be worth considering. After all, there are plenty of difficulties with issuing new DSM VLSI chip designs without significant rework and, with the continuous reduction in minimum layout geometries, the situation will become much more challenging. In fact, it is not going too far to say that some back-end optimization will be inevitable at some time in the near future, whatever the design methodology may be.

Now that we know what type of layout manipulations are most desirable, we will discuss commercially available tools capable of the following:

  1. Tools exist for retargeting existing chips. We will suggest two: one for limited hierarchical maintenance in Hard IP migration; another for fully hierarchical migration.
  2. Next we will suggest a tool allowing productive Hard IP creation.
  3. We will then suggest tools that allow transistor geometries to be analyzed and adjusted for optimal performance.
  4. Finally, we will suggest a tool focusing on spreading out interconnects to minimize capacitive coupling and improve yield.

The weakness in terms of commercial tools is really on the analysis side. Compaction allows any kind of layout adjustment we demand of the compactor. The problem lies with not knowing what the best layout geometry would be. Transistors can be adjusted because there are analysis tools to determine how much. Interconnects can be spread out to minimize capacitive coupling by simply using all the available space without increasing the total chip area. This can be done without any detailed analysis, although analysis would be very helpful. The ultimate performance, however, is achieved when analyzing the best combination of transistor size together with the load, the interconnect, it is driving. No commercial tool today addresses their simultaneous adjustments for optimal performance.

We will now look at commercial tools that help with Hard IP retargeting, Hard IP creation by enforcing layout rules with compaction, Hard IP optimization with the limited focus on transistor size optimization and reduction of capacitive coupling through wire spreading of global interconnects also affecting yield. The combination of these tools also allows the suggested DfM optimizations. For DfM it is not so much a particular tool that is needed but rather close cooperation between the processing and the design staff.