CHAPTER 3

Power considerations in sub-micron digital CMOS


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3.1. Introduction

Reliability and power considerations in scaled down processes for digital applications point towards lower and lower supply voltages [1] as explained in the previous chapter. The context in which analog functionality has to be integrated is a sub-micron, digital process. This process is optimized for digital solutions regardless the need of integration on chip of analog functionality. For analog functions, the reduction of supply voltages has a negative influence on dynamic range and power dissipation [2], [3], [4]. In this chapter it is shown that low voltage is incompatible with low power when analog signal processing circuits are being considered.

Analog designers have to cope with second order effects generated by the incompatibility of the process with analog performance. This makes the process of designing circuits a difficult task since most of the solutions valid for large supply voltages are not anymore useful due to the low voltage limitations. In many cases this yields an increase in power consumption to cope with those requirements. Although performance-critical analog circuits require a higher supply voltage it is important to design low-voltage amplifiers, data converters, filters and understand the ultimate limits for power, dynamic range and linearity [5], [6], [7], [8]. Very low power circuits have to sacrifice dynamic range, linearity or accuracy. We will focus on analog functions with high demands on accuracy, dynamic range and linearity where low-power design means to fit exactly the design within specifications with minimum power.

A designer wants a certain dynamic range and speed with a given accuracy, gain and linearity. Low voltage and low power are imposed by the application and the mixed level context. The fundamental limits for low-power in analog are asymptotic limits [2], [3]. They are combining in one simple equation power, S/N ratios and speed. There are no restrictions regarding topology, voltage swings, circuit topology, noise generated by active circuits, the process constants and linearity. By using a simple scaling rule [9], it is possible to travel along the asymptotic line without knowing whether the circuit is power optimal or not. Practical circuits show that power dissipation is dominated by the current needed to bias the active elements and has values few orders of magnitude larger than fundamental limits. That is why it is important to know practical limits of circuits and to use them in comparing different possible solutions.

Starting from general considerations and simple circuits, it is possible to prove that DR*Speed product is limited by power, topology and supply voltage regardless of the type of circuits: continuous time or sampled data, current-mode or voltage mode. Only white noise is taken into considerations. Substrate noise and 1/f noise are discussed in the next chapters. In some applications matching imposes restrictions on the obtainable accuracy [10]. Accuracy driven power gives stronger limits for power consumption. That is why, some discussions about matching driven power are mandatory. Further details concerning matching will be discussed in the next chapters.

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