Hardware debugger for the world’s fastest 8051 & 80251

Digital Core Design, an IP Core provider and a System-on-Chip design house from Poland, has recently informed about its world’s fastest 8051 & 80251 CPUs. To enable engineers even better experience with these unique solution, the company introduced a non-intrusive hardware debugger for DQ8051 and DQ80251. The system is called DoCDTM (DCD’s on-Chip Debugger) and consists of the Debug IP Core, Hardware Assisted Debugger and Debug Software. It features inter alia instruction smart trace buffer (configurable up to 8192 levels), hardware debugging, software simulation and verification.

Poland, Bytom, July the 1st, 2015.DoCDTM provides some serviceable features like a  real-time and non-intrusive debug capability, enabling a pre-silicon validation and post-silicon, on-chip software debugging. It allows hardware breakpoints, trace, variables watch and multi C sources debugging. - The DoCDTM Debug Software can work as a hardware debugger, as well as a software simulator – explains Tomasz Krzyzak, vice-president at Digital Core Design - some tasks can be validated at software simulation level and after this step, it can continue real-time debugging by uploading code into silicon.

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Digital Core Design, an IP Core provider and a System-on-Chip design house from Poland, has recently informed about its world’s fastest 8051 & 80251 CPUs. To enable engineers even better experience with these unique solution, the company introduced a non-intrusive hardware debugger for DQ8051 and DQ80251. The system is called DoCDTM (DCD’s on-Chip Debugger) and consists of the Debug IP Core, Hardware Assisted Debugger and Debug Software. It features inter alia instruction smart trace buffer (configurable up to 8192 levels), hardware debugging, software simulation and verification.The DoCDTM user can choose favorite C compilers or assemblers for software development - it supports most of High Level Object files produced by C/ASM compiler tools:
  •  Extended OMF-51 produced by Keil compiler
  •  IAR EWB 8051 & 80390 workbench
  •  OMF-51 produced by Taskingcompiler
  •  Standard OMF-51 produced by some 8051 compilers
  •  Extended OMF-251 produced by Keil compiler
  •  NOI format file produced by SDCC-51 compiler
  •  Intel HEX-51 format produced by each 8051 compiler
  •  Intel HEX-386 format produced by each 80390 & 80251 compiler
  •  BIN format produced by each 8051 & 80390 & 80251 compiler
System-on-Chip designs are facing a problem of inaccessibility of important control and bus signals, because they often lay behind the physical pins of the device - that makes traditional measurement instrumentation useless. The best way to get around those limitations is to use on-chip debug tools for the tasks verification and software debugging. Other advantage of on-chip debugger is its improved design productivity in an integrated environment, with graphical user's interface. Ability to display/modify memories' content, processor's and peripherals' register windows, along with information tracing and ability to see the related C/ASM source code, are the key elements, that help to improve the design process and thereby, to increase productivity.The  DoCDTM Hardware Debugger provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCDTM provides non-intrusive debugging of a running application. It can also efficiently save designer’s time, thanks to hardware trace, called Instructions Smart Trace buffer (IST). The DoCD-IST captures instructions in a smart and non-intrusive way, so it doesn’t capture addresses of all executed instructions, but only these related to the start of tracing, conditional jumps and interrupts. This method does not only save time, but also allows improving size of the IST buffer and extend the trace history. Captured instructions are read back by the DoCD-debug software, analyzed and then presented to the user as an ASM code and related C lines.
 
The reason for the development of the DoCDTM, was to provide our customers with the ability of easy system verification and software debugging, at no additional charges – adds Tomasz Krzyzak from DCD - Therefore, we have decided to add the complete debug system to each 8051/80251/80390 IP Core - for free.Now DCD's customers have the exceptional possibility, to obtain  the complete solution for making their own 8051 & 80251 based SoC, with the ability of pre-silicon validation and post-silicon software debugging -  in one place. It's really unusual opportunity for the designer, to have the ability to get a high quality IP Core and unique on-chip debug tool, from the same supplier.The system consists of three major blocks: Debug IP Core
  • The Debug IP Core is a real-time hardware debugger, which provides an access to all chip registers, memories and peripherals, connected to DCD's IP Core (Dx8051/DQ80251/Dx80390). It controls CPU work, by non-intrusive method. The Debug IP Core is provided as Verilog or VHDL source code, as well as FPGA netlist
  • depending on the customer requirements. The DoCDTM provides a scaled solution - many SoC designs have both power and area limitations. Debug IP Core, can be scaled to control its gate count. The benefit is fewer gates - for lower use of power and core size, while maintaining excellent debug abilities. Typically, all of the features are utilized in pre-silicon debug (i.e. hardware debugging or FPGA evaluation), with less features availed in the final silicon.
    • Processor execution control
      • Run, Halt
      • Reset
      • Step into instruction
      • Skip instruction
    • Read-write all processor contents
      • Program Counter (PC)
      • Program Memory
      • Internal (direct) Data Memory
      • Special Function Registers (SFRs)
      • External Data Memory
    • Code execution breakpoints
      • up to eight real-time PC breakpoints
      • unlimited number of real-time OPCODE breakpoints
    • Hardware execution watch-points
      • two at Internal (direct) Data Memory
      • two at Special Function Registers (SFRs)
      • two at External Data Memory
    • Hardware watch-points activated at a
      • certain address by any write into memory
      • certain address by any read from memory
      • certain address by write into memory a required data
      • certain address by read from memory a required data
    • Unlimited number of software watch-points
      • Internal (direct) Data Memory
      • Special Function Registers (SFRs)
      • External Data Memory
    • Unlimited number of software breakpoints
      • Program Memory
    • Instructions Smart Trace Buffer – configurable up to 8192 levels (optional)
    • Automatic adjustment of debug data transfer speed rate between HAD2 and Silicon
    • Communication interface
      • TTAG two-wire communication or
      • JTAG interface
    • Fully static synchronous design with no internal tri-states
Debugger Software
  • The DoCDTM Software (DS) is a Windows based application. It is fully compatible with all existing 8051/80251/80390 C compilers and Assemblers. The DS was designed to work in two major modes: software simulator mode and hardware debugger mode. Those two modes, allow the pre-silicon software validation in simulation mode and then, real-time debugging of developed software inside silicon - using debugger mode. Once loaded, the program may be observed in Source Window, run at full-speed, single stepped by machine or C-level instructions or stopped at any of the breakpoints. The DoCD TM Debug Software, supports all DCD's 8051/80251/80390 Microcontroller Cores, with their particular configurations
    • In-system FLASH programming
    • Two working modes
      • hardware debugger
      • software simulator
    • Source Level Debugging:
      • C level hardware/software breakpoints
      • C code execution
        • line by line
        • over line
        • out of function
        • skip line
      • ASM code execution
        • instruction by instruction
        • over instruction
        • out of function
        • skip instruction
      • ASM, C source view of code
    • Symbol Explorer provides hierarchical tree view of all symbols:
      • modules
      • functions
      • blocks
      • variables and more
    • Contents sensitive Watch window
    • Symbolic debug including:
      • code
      • variables
      • variable types
    • Unlimited number of Real-time hardware breakpoints
      • Program Memory (CODE)
    • Two real-time hardware watch-points for each space:
      • Internal (direct) Data Memory (IDM)
      • Special Function Registers (SFR)
      • eXternal Data Memory (XDM)
      • Unlimited number of software breakpoints
        • Program Memory
        • Internal (direct) Data Memory (IDM)
        • Special Function Registers (SFR)
        • eXternal Data Memory (XDM)
      • Set/clear software or hardware breakpoints, watch-points in Disassembled and C Source Code windows
      • 1024 steps deep Software Trace
      • Load Program Memory content from:
        • OMF-51, extended OMF-51 files
        • OMF-251 file
        • Intel HEX-51, HEX-386 files
        • BIN file
    • Auto refresh of all windows, during execution of program
      • Registers panel including ACC, B, PSW, PC, SP, DPTR, DPP and four banks of general purpose registers (R0-R7)
      • Internal (direct) Data Memory (IDM)
      • Special Function Registers (SFR)
      • eXternal Data Memory (XDM)
      • Timers/Counters
      • UARTs
      • I/O Ports
    • Dedicated windows for peripherals
    • Configurable auto refresh time period
    • Status bar containing number of actually executed instructions, number of clock periods and real processor speed rate
    • Hardware Assisted Debugger interface
      • TTAG two-wire interface
      • JTAG interface
    • The system runs on a Windows 2000/2003/XP/7/8/8.1 (both 32 and 64 bits) PC
    • Supports software tools from Keil, Archimedes, IAR, Tasking, Franklin, SDCC and the others
Hardware Assisted Debugger
  • A high-performance Hardware Assisted Debugger is connected to the target system, containing the DCD's core, either in FPGA or ASIC. HAD2 is a small hardware adapter, that manages communication between the Debug IP Core (JTAG/TTAG/DTAG protocols) inside silicon and a USB port of the host PC, running DoCD TM Debug Software.
  • USB 2.0 communication interface to target host
  • Synchronous communication interface to Debug IP Core
    • TTAG two-wire communication
    • JTAG interface
    • DTAG three wire interface
    • Support four I/O voltage standards
      • 3.3 Volt systems
      • 2.5 Volt systems
      • 1.8 Volt systems
      • Single power supply directly from USB port
      • Small physical dimensions
More information: http://dcd.pl/page/154/docd/ Information about Digital Core Design: The company founded in 1999, since the beginning stands in the forefront of the IP Core market. High specialization and profound customer service enabled to introduce more than 70 different architectures. Among them is the world’s fastest 8051 IP Core, the DQ80251, which is more than 66 times faster than the standard solution. As an effect, over 300 hundred licensees have been sold to more than 500 companies worldwide.
 
Among them are the biggest enterprises like e.g. Sony, Siemens, General Electric and Toyota. But a lot of DCD’s customers are small businesses, R&D laboratories or front/back end offices, which require exact solution tailored to their project needs. Rough estimations say that more than 270 000 000 devices around the globe have been based on Digital Core Design’s IP Cores.
 



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