Synfora CTO to Give Tutorial on Reducing Design Time with Algorithmic Synthesis at ESC Silicon Valley

MOUNTAIN VIEW, Calif.—(BUSINESS WIRE)—March 24, 2009— At the Embedded Systems Conference (ESC) on March 31, 2009, in San Jose, California, Vinod Kathail, Chief Technology Officer at Synfora, Inc., will be giving a tutorial on algorithmic synthesis tools and methodologies that allow the design and verification of application accelerators directly from sequential C algorithms.


The presentation, “Algorithmic Synthesis of Application Engines from C/C++ Algorithms,” will be given at 8:00 AM as part of the “Improve Productivity at the HW/SW Interface” track. It will discuss the use of algorithmic synthesis to design complex, multi-block application accelerators and their associated bus/memory/stream interconnects from C algorithms, including the verification and system validation of the resulting RTL.


  Synfora, Inc.


  Technical presentation on using algorithmic synthesis to reduce design and verification time of multi-block application accelerators


  Tuesday, March 31, 2009, 8:00 AM -- 9:15 AM


  Embedded Systems Conference (ESC) Silicon Valley 2009
    McEnery Convention Center
    San Jose, California
    Room C3

The ESC Silicon Valley 2009 is being held March 30 – April 2 at the McEnery Convention Center in San Jose, California.

About Synfora, Inc.

Synfora, Inc. is the premier provider of algorithmic synthesis tools used to design complex systems-on-chips (SoCs) and FPGAs. Synfora's technology helps to reduce design costs, dramatically speed chip development, and reduce time-to-market. Synfora serves customers worldwide in the audio, video, imaging, wireless, and security segments of the integrated circuit (IC) design market. The company's investors are ATA Ventures, Foundation Capital, U.S. Venture Partners, Wafra, and Xilinx. For the latest information on Synfora, please visit



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