Logic Design for Array-Based Circuits - D. E. White - eBook


Logic Design for Array-Based Circuits by Donnamaie E. White Copyright © 1996, 2001, 2002 Donnamaie E. White

Table of Contents Preface Overview Chapter 1 Introduction Chapter 2 Structured Design Methodology Chapter 3 Sizing the Design Functional Specification - A Closer Look Review the Available Arrays Architectual Specification or Hardware Specification Array Sizing Cell Capabilities Array Architecture Netlist Example: AMCC Interface Options Example - AMCC Arrays - Power Supply Options Interface Cell Functionality Examples Internal Cell Functionality Multi-Cell Macros Hard and soft macros Refining Interface Requirements Adding Extra Power and Ground Macros Dual-Function I/O Macros Example - Simultaneously Switching Outputs Thermal Diodes The AMCC Speed Monitor Final Interface Cell Utilization Drivers Exercises Chapter 3 Appendix: Case Study in Sizing a Design Target Array: AMCC Q20080 (1994 Data) Solution - Q20000 Selecting a Flip/Flop - First Pass Selecting the ECL Output Clock Input 16:1 MUX Parity Tree Review Status so far Exercise Simultaneouly Switching Outputs Fanout Loads Select Lines for 16:1 MUX Reset Loading Clock Static Driver Review of Size - Second Pass Package Size Problems Alternative Solution Power Further Thought The Schematics Chapter 4 Design Optimization Chapter 5 Timing Analysis for Arrays Chapter 6 External Set-up and Hold Times Chapter 7 Power Considerations Case Study: DC Power Computation Case Study: AC Power Computation Chapter 8 Simulation Case Study: Simulation Chapter 9 Faults and Fault Detection Chapter 10 Design Submission ASIC Glossary Glossary A-D Glossary E-K Glossary L-R Glossary S-Z Symbols	Case Study: Sizing A Design Last Edit July 22, 2001 TARGET ARRAY: AMCC's Q20080 {Based on 1994 data} The following exercise is not intended as a practical circuit for actual construction on an array, however, this exercise will examine nearly every design rule and restriction for the example array series. It will be solved here using a Q20080 array as the intended target solution but could be solved with any macro library provided one of the supported arrays in that series can accommodate approx. 160 I/O signals and toggle at 500MHz. See Figure A-1. Figure A-1 Sample Classroom Exercise THE DESIGN Using the following list of requirements, design a circuit using AMCC macros for the Q20000 Series and size the design to fit the Q20080 array in that series: A pipelined structure two flip/flops deep is to be 32 bits wide. Each data input to the first flip/flop stage is to be driven by a 2:1 MUX, the inputs of which are driven by ECL 10KH inputs. All flip/flops are required to be reset by way of a master reset signal. The common clock is to be a differential signal, if possible. All 32 multiplexors are to have a common select. The target maximum speed of operation is 500MHz. (Design Objective.) All dataA inputs (32 of them) are to be fed in groups of four into two 16:1 multiplexors. There are four common select lines for the two 16:1 multiplexors and two outputs, controlled by enables (one per signal). All input signals, data and controls, are to be fed into a parity tree, a gate tree that will produce a single output. This structure is to be used for parametric testing. A six-bit pass-through bus (input to output without logic) is included which uses ECL inputs and outputs. The flip/flop output stage is connected to non-Darlington ECL 10KH outputs. Both true and complementary outputs are to be brought out to external pins. This is a military, standard reference ECL -5.2V single-supply circuit. Note: Keep your data. This problem or a similar one will be referred to in other chapters. Exercise Review the selected design manual, select macros and compute cell utilization. Pick an array from the series that would fit the design. Perform all required population checking for that series.
Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises For problems or questions on these pages, contact dew@Donnamaie.com