Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002 Donnamaie E. White

• Table of Contents
  
• Preface
  
• Overview
  
• Chapter 1 Introduction
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
  • Functional Specification - A Closer Look
  • Review the Available Arrays
  • Architectual Specification or Hardware Specification
  • Array Sizing
  • Cell Capabilities
  • Array Architecture
  • Netlist
  • Example: AMCC Interface Options
  • Example - AMCC Arrays - Power Supply Options
  • Interface Cell Functionality
  • Examples
  • Internal Cell Functionality
  • Multi-Cell Macros
  • Hard and soft macros
  • Refining Interface Requirements
  • Adding Extra Power and Ground Macros
  • Dual-Function I/O Macros
  • Example - Simultaneously Switching Outputs
  • Thermal Diodes
  • The AMCC Speed Monitor
  • Final Interface Cell Utilization
  • Drivers
  • Exercises
• Chapter 3 Appendix: Case Study in Sizing a Design
  • Target Array: AMCC Q20080 (1994 Data)
  • Solution - Q20000
  • Selecting a Flip/Flop - First Pass
  • Selecting the ECL Output
  • Clock Input
  • 16:1 MUX
  • Parity Tree
  • Review Status so far
  • Exercise
  • Simultaneouly Switching Outputs
  • Fanout Loads
    • Select Lines for 16:1 MUX
    • Reset Loading
    • Clock
    • Static Driver
  • Review of Size - Second Pass
  • Package Size
  • Problems
  • Alternative Solution
  • Power
  • Further Thought
  • The Schematics
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulation
• Chapter 9 Faults and Fault Detection
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Case Study: Sizing A Design

Last Edit July 22, 2001

REVIEW STATUS SO FAR

The first sizing estimate provides the cell counts shown in Table A-2.

Table A-2 First Sizing Estimates

TOTAL I/O CELLS: 153

TOTAL L CELLS: 245

The number of macros is not the same as the number of cells, even for the I/O macros.

Exercise

Check the cell counts against the current design manual for the Q20000 Series. Check for new MSI macros or new I/O macros that might be used in place of those selected (such as OE11S). Consider size, speed and power in making changes. (Changes should be made!)

If you are designing with a different array series, create the same table for the chosen library.

SIMULTANEOUSLY SWITCHING OUTPUTS

Since 64 outputs are switching simultaneously in the worst case (master reset is one example), additional IEVCC macros (added ground) will be required according to the Q20000 Series design rules. A total of 16 IEVCC macros is required for these outputs and each blocks off one I/O cell and uses one pad.

This is the minimum number of added power and grounds recommended for worst-case conditions.

Adding two more outputs for the 16:1 MUX Y outputs, six for the pass-through and one for the gate tree, requires two more IEVCC macros.

• If the outputs switch within one macro delay (or within 2 ns, whichever is larger) of the other switching group additional IEVCC is required.
• If they switch well separated in time from the other group, then the added IEVCC for this group will not be required.

By tagging the switching groups and the added power and ground macros that belong to the groups with a SWGROUP parameter or property, the AMCC MacroMatrix can check for sufficient added power and grounds.

For this design, assume that the groups are not simultaneously switching more than 32 signals, allowing a reduction in added ground. Allowing 8 IEVCC for the pipeline outputs (switching group AAA) and one for the rest of the circuit (switching group BBB), nine IEVCC macros are required.

Adding these 9 IEVCC macros to the previous counts (153 + 9), the number of I/O cells used is 162. This is exactly the number of I/O cells available for circuit use on the Q20080 array. (This does not count the four fixed I/O signals for the AC Speed Monitor and the thermal diode that have pre-assigned PADs.) The added ground macro is shown in Figure A-9.

Figure A-9 Added IEVCC Macro

Note: Using less than the recommended number of added grounds is not a good idea. It will require engineering approval before design submission and could cause other problems later. Think about another solution!

Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises
For problems or questions on these pages, contact dew@Donnamaie.com