Case Study: Sizing A Design
Last Edit July 22, 2001
THE SCHEMATICS
Page 1 - Chip Macro and added Ground (IEVCC for ECL VCC);
AAA is switch group tag; GT87D a static driver
Page 2 - Clock tree; RESET tree; 2:1 MUX select tree. Buffer trees go
to various pages. Note the inputs to the parametric gate tree. "40"s
are FOD values. (Figure A-10, Figure
A-11, Figure A-12, Figure
A-13)
Page 3 - 2:1 MUX selects and enable controls; 6-bit input-output path.
OE42S macros should be replaced and VLO signal deleted.
Page 4 - Using MX21S 4:1 MUX macros to built a 16:1 MUX. OE42 should be
changed.
Page 5 - pipelined register: 2:1 MUX-D F/F FF46S feeds FF10S which drives
OE14S. OE14S connection could be improved to remove need for VLO signal.
Page 6 - Same as page 5 except for names. Note output to parametric gate
tree. AAA is the switch group tag (matches IEVCC on page 1).
Page 7 - Next four bits.
Page 8 - Next four bits.
Page 9 - Next four bits. Note how the page number has been incorporated
into the macro instance names - FF0905, FF0906, etc. - to prevent duplicate
names.
Page 10 - Next four bits.
Page 11 - Next four bits.
Page 12 - Last four bits for 32-bit registers.
Page 13 - The parametric gate tree - all inputs fed into a combinatorial
gate tree and tied to one output. PGATE is the GTO parameter value. OE42S
should be changed. Note how page references make it possible to trace
the connections. (Figure A-8)
Page 14 - The second 16:1 MUX - this page should have been grouped with
the other MUX page for better schematic set readability. Group functions
together. (Figure A-7)
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