Logic Design for Array-Based Circuits


Logic Design for Array-Based Circuits by Donnamaie E. White Copyright © 1996, 2001, 2002 Donnamaie E. White

Table of Contents Preface Overview Introduction Integration Levels Demand and Supply eLearning - the Next Best Thing Chapter 1 Introduction Chapter 2 Structured Design Methodology Chapter 3 Sizing the Design Chapter 3 Appendix = Case Study in Sizing a Design Chapter 4 Design Optimization Chapter 5 Timing Analysis for Arrays Chapter 6 External Set-up and Hold Times Chapter 7 Power Considerations Case Study: DC Power Computation Case Study: AC Power Computation Chapter 8 Simulation Case Study: Simulation Chapter 9 Faults and Fault Detection Chapter 10 Design Submission ASIC Glossary Glossary A-D Glossary E-K Glossary L-R Glossary S-Z Symbols	The original form of this book was published by Academic Press, 1250 Sixth Avenue, San Diego, California 92101-4311 in 1992. ISBN 0-12-746660-6. The figures were reproduced with the permission of Applied Micro Circuit Corporation. The Q20000 Series and other bopolar and BiCMOS series referenced belong to AMCC. EPAC is a trademark of IMP, Inc. The original form of this book was based on classes taught at USCD and at AMCC's customer Design Center and focused on the AMCC ASIC arrays (the Q20000 Bipolar and Q24000 BiCMOS array series) as specific examples of a general structured design methodology. Customer training courses prepared by high-technology vendors are a required extension to that training available in the engineering classes at the college level. The quality of that training can vary with the experience of the instructor. The experience of the instructor with the nuances of the products is one facet. The teaching expertise is another. The purpose behind the original form of this book was to document what a proven instructor was adding to the course material and manuals. By providing this supplement, it would be possible for other, less experienced instructors, to take over the actual presentation of the seminars while ensuring no loss of insight into the methodology or product taught. The edited material will be uploaded as text first and then interwoven with additional sites and pages. This is an on-going evaluation of the Internet as a teaching tool. Table of Contents Preface Overview Introduction Integration Levels Demand and Supply eLearning - the Next Best Thing Chapter 1 Introduction Introduction Selection Design Support Issues Schematic Rules Checking Reformatters Design Upgrades Exercises Update 2000 Chapter 2 Structured Design Methodology Structured Design Methodology Review of the Available Arrays Initial Sizing of the Circuit Create the Preliminary Macro Schematic (when schematics are used) Compute the Path Propagation Delay Compute the Estimated Power Pre-Simultation Steps Simulation Fault Grading Design Submission Through Prototype Design Validation Review Placement Chapter 3 Sizing the Design Functional Specification - A Closer Look Review the Available Arrays Architectual Specification or Hardware Specification Array Sizing Cell Capabilities Array Architecture Netlist Example - AMCC Arrays - Power Supply Options Examples Refining Interface Requirements Dual-Function I/O Macros Thermal Diodes Final Interface Cell Utilization Drivers Exercises Chapter 3 Appendix = Case Study in Sizing a Design Chapter 4 Design Optimization Introduction Optimization Approaches Design to Improve Speed Example of Silicon Efficiency Internal Net Delays Design to Reduce Internal Cell Utilization Design to Reduce I/O Utilization Design to Fit the Package Design to Reduce Power Design to Reduce Cost Basic Design for Circuit Testability Basic Design for Circuit Reliability Design to Reduce Cost Exercises Chapter 5 Timing Analysis for Arrays Introduction Path Propagation Delay Overview Intrinsic Set-Up and Hold Time Interconnect Delays Annotation Manual Computation - One Method Example Equations for Extrinsic Loading - Internal Nets k-Factors Computing Lfo Computing Lwo Computing Lnet Example Equations for Extrinsic Loading - Output Nets Worst-Case Delay Multiplication Factors Front Annotation Intermediate Annotation Back Annotation Exercises Chapter 6 External Set-up and Hold Times Introduction Case 1: When the Timing Specifications Are Nominal Case 2: When The Timing Specifications Are Worst-Case Example - AMCC Q1400 BiCMOS Series Example - AMCC Q20000 Bipolar Series Case Study: Preventing Hold Violations Due To Clock Skew Computing Hold Time in the Register Example Chapter 7 Power Considerations Introduction DC Power--- AC Power Worst-Case Power Power Reduction Techniques Design Rules for Power Reduction (AMCC) Computing DC Power Dissipation AC Macro Power Dissipation Case Study: DC Power Computation Step 10: Determine ECL Static Power PEO Case Study: AC Power Computation Total Power Dissipation Chapter 8 Simulation Introduction Simulators - The Tools Wafer Sort/Packages Part Sort Functional Simulation At-Speed Simulation For Timing Verification AC Tests Parametric Vectors Hazards Case Study: Simulation Functional Simulation Parametric Simulation At-Speed Simulation AC Test Chapter 9 Faults and Fault Detection Introduction Fault Types The Problem Selecting a Chain Case Study - 16:1 MUX 2:1 MUX Example 3:1 MUX Actual Test Vector Sequence for a 16:1 MUX with Clocked Output Chapter 10 Design Submission Case Study: AMCC Design Submission Continued Functional Simulation Submission (Required) At-Speed Simulation Submission (Required) AC Tests Path Delay Vector Submission (Optional) Parametric Vectors (Required or Optional) ASIC Glossary Glossary A-D Glossary E-K Glossary L-R Glossary S-Z Symbols
Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises For problems or questions on these pages, contact dew@Donnamaie.com

by Donnamaie E. White