Logic Design for Array-Based Circuits

by Donnamaie E. White

Copyright © 1996 Donnamaie E. White
Last Edit September 11, 1996

Chapter 2 Continued

The Design Submission Through Prototype

Complete the design validation review

Once the simulations are completed, the entire circuit package should be reviewed for completeness. This is a preliminary design acceptance review.

AMCC currently provides a Design Validation form that identifies areas that are characteristically problems in a design submission, a list of items that previous design submissions had in error.

After AMCCERC errors, timing check errors and AMCCVRC errors have been resolved, the designer should work through the checks in the Design Validation section of the design manual. These are checks that have not yet been or can never be automated. The questionnaire is incorporated into AMCCSUBMIT, a design submission program that queries the designer for file names and conditions, and produces reports for use in design submission.

For array vendors without such a list or automated support, review the submission procedures and the array design rules.

Complete the design submission checklist

The array vendor will have a submission procedure, a list of the files and documents required for submission before the vendor can accept the design and proceed to layout.

Check off the required items as they are assembled into the package. A design cannot be submitted without the completion of the required items. Optional items must be complete if the option is chosen. Last of all, make sure some media index exists in both media and hardcopy form that identifies what is in the submission package.

AMCC has created a generic design submission form as a first step in creating a user-interface automation of the design submission - design validation process. It and its accompanying document detail what is required to be submitted in hardcopy and what is to be submitted on media (disk or tape). (The first version of the form is now part of AMCCSUBMIT.)

AMCCSUBMIT generates a report that alerts the reviewer to problem areas in the design or the design submission package.

Submit the circuit - acceptance design review

When the design submission package is complete, submit it. The vendor will review the package for completeness and correctness. The submission will include all pre-approved design waivers negotiated before submission.

  • If everything has been done according to the vendor's rules, the design will be accepted and move into its proposed schedule.

  • If only minor things are missing or incorrect, the array vendor may make the changes under the designer's approval.

  • If serious errors or omissions exist, the design may be rejected, i.e., returned to the designer with instructions on what is missing or incorrect.

Implementation Engineering - the Array Vendor

On design acceptance, the Implementation Engineer assigned to the design will rerun all simulations against the in-house library. The object is to identify any macro design changes implemented after the library release date that would affect the design under review.

A second objective is to verify that the circuit used on the schematics, netlist and simulations all match since it is easy to violate file consistency.


After processing by Implementation Engineering, the circuit will be submitted for layout. Preplacement requests that were approved by the array vendor are input to the layout system in this phase. For customers who wish a particular package pin-out, a specific pad placement may be required. Vendors attempt to honor these requests if they do not violate other placement criteria.

Placement restrictions may be I/O mode and package specific. They may be driven by the type of macro, such as the dual-cell differentials. They may be driven by MSI (multiple-cell) placement requirements, whether these are hard or soft macros. Timing specifications and clock distribution requirements are another factor as are the particular restrictions induced by simultaneously switching outputs (SSO).

Packages that use internal power and ground planes may restrict where added power and ground macros are placed, and this may conflict with the SSO requirements.

All of these factors must be reviewed before approving a placement.

A placement is not usually considered final until after routing and then only after the at-speed Back-Annotated simulation is approved by the customer. On the average, a circuit requires a first-pass placement (90-95% auto-placement is the goal) and some adjustments in a second pass.

- Intermediate Annotation

Some vendors may have an Intermediate-Annotation software package capable of providing Manhattan-Distance algorithm-based Intermediate Annotation delay files. They allow simulations to be performed with time delay data that is much closer to reality than the generic, "every-same-sized-net-is-the-same-length" Front-Annotation software.

For a circuit where the technology is being pushed to the limit, and Back-Annotation will take more than a week to obtain, it might be a good idea to run Intermediate-Annotation simulations. They are still not accurate enough to be treated as a specification, but they could identify gross errors in placement that could be corrected before routing.


Routing is the longer process. For circuits meeting the internal pin count and cell utilization limits for the array, 95% of the nets can usually be routed automatically. The last few are closed by a human operator at a graphics interface terminal. Some array vendors will not accept an array that cannot be 95% autorouted.

As a guideline, AMCCERC will report warnings for those circuits exceeding recommended internal cell utilization limits and recommended internal pin count limits. It will report an error for those circuits that exceed the limits so far as to be considered impossible to route. It cannot cross-check package pad-pin requirements or make any assumptions about the physical location of the macros.

- Back-Annotation

After layout, the Back-Annotation delay files are available to the designer to rerun the logical and at-speed simulations, plus any of the optional simulations originally submitted. These files provide the actual metal lengths in the circuit nets as opposed to the estimated metal length, and the actual (as far as is known) package pin capacitance for the output nets.

Critical paths must be checked with this data. At this point, a failure to meet specification timing requirements by a small amount may be correctable with a layout adjustment or a routing change. Serious failures may signal the need to re-design.

AMCC and most vendors guarantee the maximum worst-case Back-Annotation at-speed simulation, i.e., guarantee that the silicon will not be slower than the results.

The careful evaluation of the critical paths early in the design phase, the proper derating of the fan-out loading, careful selection of the macros and the options for those macros, preplacement for critical and sensitive paths (balanced against the placement restrictions and rules for the array), and the careful simulation and timing validation before layout, will all ensure a successful design experience.

Re-simulation and timing validation after layout (place and route) help ensure a successful wafer.


After the Back-Annotated simulations are approved by the customer, the vendor can proceed to produce prototypes.

Array Design Acceptance

After prototyping and testing per the testing specification supplied at design submission, including the functional vectors, the customer would perform the final array acceptance as desired. At this point, full fabrication of the final product can begin.

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Copyright © September 1996, July 1998 Donnamaie E. White