Logic Design for Array-Based Circuits
by Donnamaie E. White
Copyright © 1996, 2001, 2002 Donnamaie E. White
- Table of Contents
- Preface
- Overview
- Chapter 1 Introduction
- Chapter 2 Structured
Design Methodology
- Structured Design Methodology
- Review of the Available Arrays
- Initial Sizing of the Circuit
- Create the Preliminary Macro Schematic (when schematics are used)
- Compute the Path Propagation Delay
- Compute the Estimated Power
- Pre-Simultation Steps
- Simulation
- Fault Grading
- Design Submission Through Prototype
- Chapter 3 Sizing the Design
- Chapter 3 Appendix = Case Study in Sizing a Design
- Chapter 4 Design Optimization
- Chapter 5 Timing Analysis for Arrays
- Chapter 6 External Set-up and Hold Times
- Chapter 7 Power Considerations
- Case Study: DC Power Computation
- Case Study: AC Power Computation
- Chapter 8 Simulation
- Case Study: Simulationest
- Chapter 9 Faults and Fault Detectiond Output
- Chapter 10 Design Submission
- ASIC Glossary
Structured Design Methodology
Last Edit July 22, 2001
Review of the available arrays
The arrays available at the time of a design evaluation need to be reviewed using the outline in Table 2-3 as an initial basis of comparison.
Table 2-3 Array Checklist - Initial Review
| Initial Review Checklist |
|---|
| technology |
| I/O resources - number of available I/O pads and pins |
| internal density or equivalent gate limits |
| I/O mode configurations including power supplies supported |
| Placement support, options |
| power dissipation limits |
| available packaging |
maximum operating frequencies
|
design support:
|
| turnaround time from design submission to wafer prototype |
| cost |
Figure 2-1 indicates the interdependencies between functional specification, hardware specification and the arrays.
Figure 2-1 The Array Selection Process
This review must compare what is available with the circuit specifications and produce a list of the available arrays that could be used to support those specifications. As the number of potential arrays is reduced, preliminary implementations of some of the critical paths for the circuit, constructed from the macro libraries under consideration, should be evaluated.
Historical Table of Commerecial, Military Libraries, Power Supplies for One Array Series
Copyright @ 2001,
2002 Donnamaie E. White, White
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