Logic Design for Array-Based Circuits
by Donnamaie E. White
Copyright © 1996, 2001, 2002 Donnamaie E. White
Last Edit July 22, 2001
Design To Reduce I/O Utilization
There are several techniques used to reduce the I/O cell utilization shown in Table 4-7.
Table 4-7 Reducing I/O Cell And Pad Utilization
The difficulty with array-based circuit design is that, should a circuit require just one more I/O connection, there is no way to obtain it save by the selection of a larger array. There are no jumpers, piggy-backed components and other quick-and-dirty board design tricks that can apply. The I/O signal count must fit the target array, and be equal to or less than the available array signal pads.
Copyright @ 2001,
2002 Donnamaie E. White, White