Logic Design for Array-Based Circuits

by Donnamaie E. White

Copyright © 1996, 2001, 2002 Donnamaie E. White


Design Optimization

Last Edit July 22, 2001

Design To Reduce Cost

The cost of a design is a function of all factors involved in that design, from the initial design decisions on who will do the macro conversion to the special testing requirements. Anything that is not within the standard, routine design flow will usually cost more. Design iterations cost more. A redesign averages the same amount of CPU time spent in simulation.

Items that increase costs are listed in Table 4-9. Some guidelines to keep costs down are shown in Table 4-10 .

Table 4-9 Items That Increase Cost; *

Items That Increase Circuit Costs
  • Training classes
    - usually credited against NRE
  • Amount of design support from vendor
    • macro conversion
    • performing validation
    • performing simulations
  • Array series chosen
  • Size of the array
  • Custom macros
  • Use of the vendor's design center longer than a nominal time
    (4 weeks)
  • Functional vectors that exceed 4K
    • charged on a per page (4K) basis (based on the
      SENTRY tester) or whatever limit is specified
  • Functional vectors that contain races and hazards
    (require rework)
  • Fault grading - more than 2 passes
  • Net matching required
  • Pre-defined pin-out (causes iterations)
  • Design iteration
    • after first place and route
    • when it was not the vendor's error
  • Non-standard bonding
  • Non-standard package
  • Optional heatsink
  • Custom DUT board
  • Custom test software
  • Bench tests
    • charged per path
  • MIL screening
    • tri-temp testing
    • burn-in
    • qual
  • Optional Commercial circuit burn-in
  • Optional Commercial circuit - qual
  • Optional PIND testing (post-package)
  • Expedite on schedule

* AMCC measures used for example

Table 4-10 Keeping The Costs Down

How to Keep Circuit Costs Down
  • Allow adequate time in the design schedule and keep to the schedule
  • Allow time for several design reviews at various steps in the design flow
  • Allow time for the vendor's steps and to review those steps
  • Follow the previously outlined steps for the design flow
  • Choose an array that is adequate for the design - within population and cell utilization bounds
  • Keep the junction temperature within bounds
    --- so that a heatsink is not required
    --- to minimize placement problems
  • Use added power and grounds as required for SSOs, high-frequency- use additional grounds
  • Keep the design modular to keep functional vector set size down
  • Plan for standard packaging, standard bonding
  • Do not commit the PCB layout until the array place and route is approved
  • Plan the design (through a design review) before showing up at the design center
  • Design for testability
  • Work with the vendor to avoid custom macros
  • Plan for standard testing, standard DUT board
  • Plan to avoid costly redesigns

Design Reviews

A design review should be held at the initial optimization at the block diagram-functional description stage of the design. Another design review should be held on the completion of the design optimization at the macro level, before any lengthy simulations are performed. This procedure will help to reduce iterations of the simulation design step.


Design optimization is not something that is just applied to a design after it has been created. Optimization should be considered as a design is being planned, as the block diagram is being sketched, and as the macro conversion is being performed. The design criteria, and the priorities of those criteria should be established at the start of the design cycle and referred to at every step in that cycle.

The design criteria are not compatible items. In satisfying one objective, another may be compromised. The engineering task is to satisfy as many as feasible for the given situation. It requires tradeoffs and compromise.


  1. Select an array series and macro library to evaluate.
  2. Choose a design project of your own or try a 16-bit adder with latched input and registered output (the adder portion of the Am2901 without memory).
  3. Establish a set of prioritized design objectives including the target array and the target speed (such as add-with-carry). Block out a solution for the design.
  4. Change the priority of the design objectives. For example, instead of speed being the most important, make cell reduction and power reduction the most important objectives. Block out a second solution for the design.
  5. What effect did this change of perspective have on your approach to the design?

Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises
For problems or questions on these pages, contact dew@Donnamaie.com