Logic Design for Array-Based Circuits

by Donnamaie E. White

Copyright © 1996, 2001, 2002 Donnamaie E. White



Last Edit July 22, 2001

Wafer Sort/Packages Part Sort Functional Simulation

The vectors used to perform wafer sort and packaged part testing are generated from simulation output vectors. These simulation output vectors consist of all the input and the expected output signals generated by the input file. These vectors provide a time independent, sequential state description of the circuit after any input change has propagated through the logic and all the outputs have settled to their stable state. A reasonable sample step for this simulation is 100ns, with the sample taken one simulator time step before the next input vector.

The simulation provided to the array vendor should contain sufficient vectors to provide verification of the logic and should supply all simulation vectors required for the recommended 90% or better fault coverage of the final circuit. The level of fault coverage will vary from vendor to vendor or may be dictated by the designer's company. Indications are that reliability requirements are beginning to force a high (98-99%) fault coverage requirement.


Fault grading is a measure of the fault coverage - a "grade" on the quality of the fault detection provided by the submitted simulation vectors. A fault grading score of 100% means that if a SA1 or SA0 fault exists at any single observable node within the circuit it will be detected during the tester functional testing phase.

Single fault detection, the detection of a stuck-at fault (SA1 = stuck-at-1; SA0 = stuck-at-0) at any single node in the circuit, requires that the node be "covered" by at least one simulation vector. A node is covered by the vector set when the state of at least one circuit primary output for at least one vector is different when the failure is present than when the failure is absent. A failure at a circuit node that is not covered by the functional simulation vector set will not be detected.

A stuck-at fault is generally thought of as a physical open or short circuit, i.e., a "hard" failure. Intermittent failure is not necessarily detectable by the stuck-at model.

Redundancy in the circuit produces fault-masking and will reduce the obtainable fault-coverage since it reduces the observable nodes. The addition of test points when the redundancy is deliberate, and the minimization of the circuit when it is not, are recommended approaches to improve testability.

There are no requirements for fault location, i.e., the identification of the exact point of failure. Multiple-fault detection, a less-probable occurrence, is also not required although most single-fault minimal test sets and minimal test sequences will provide 100% fault coverage of all observable faults and will also detect the presence of many multiple faults, depending on the circuit implementation.

The Minimal Test Sequence as applied to combinatorial and sequential circuit elements is discussed in Chapter 9.

Table 8-1 Questions To Be Asked

Questions to Ask About Simulation Submission Requirements
  • What simulations are required fordesign submission and on what media?
    • wafer-sort
    • timing verification at speed
    • AC tests
    • parametric tests
    • other
    • Electronic FTP, floppy disk or tape?
  • What simulations may be submitted?
  • What simulators are supported?
  • What support for hazard and race detection?
  • What timing verifiers are supported?
  • What level of fault-grading is required?
    • by the array vendor
    • by the designing company
  • What rules must be followed for each type of simulation
  • Determine if ATG outputs are acceptable or if they need a post-processing
  • What is submitted?
    • simulator control or command files
    • input files
    • output files
    • vector checking reports
    • netlist
    • annotation delay files
    • other control or data files?
  • Is annotation software available?
  • What testers are available?
  • What expansion can be expected from the test program?
  • What vector-checking software is available?

Testability Analysis

There were several available software packages such as the Dazix DTA (Dazix Testability Analyzer) and Tegas COPTR that analyzed the testability of a design. They attempted to measure the controllability and the observability of the nodes within the design. There are various products on individual workstations that have been designed to perform this task. Note that array vendors on the whole do not enforce their use and may not support them if different models are required.

Controllability is the measure of how difficult it is to set a node to a given value. A node is controllable if it takes one or not more than a selected number of vectors to set it to a given value, i.e., propagate a primary input signal to that node. The ideal case is that it requires one vector to set a node.

Observability is the measure of how difficult it is to see the value to which a node is set. A node is observable if it takes one or not more than a selected number of vectors to propagate the value of the node to an observable output. The ideal case is that it requires one vector to observe a node.

Design optimization using ad hoc or formal procedures (DFT) to improve testability scores were discussed earlier. If such software is available, it is recommended that the design evaluate the circuit for testability before finalizing the design and proceeding with the simulations.



Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises
For problems or questions on these pages, contact dew@Donnamaie.com