Logic Design for Array-Based Circuits


Logic Design for Array-Based Circuits by Donnamaie E. White Copyright © 1996, 2001, 2002 Donnamaie E. White

Table of Contents Preface Overview Chapter 1 Introduction Chapter 2 Structured Design Methodology Chapter 3 Sizing the Design Chapter 3 Appendix = Case Study in Sizing a Design Chapter 4 Design Optimization Chapter 5 Timing Analysis for Arrays Chapter 6 External Set-up and Hold Times Chapter 7 Power Considerations Case Study: DC Power Computation Steps Required to Compute DC Power - Example Array Series Build the Macro Occurence Table Find the Tital Interface Macro Current Computer the Worst-Case Interface Current Compute the Total Typical Internal Macro Current Compute the Worst-Case Internal Current Compute the Total Typical Overhead Current Compute the Worst-Case Overhead Current Sum the ICC and IEE Currents Multiply by Worst-Case Voltage Determine ECL Static Power PEO ECL Output Termination Current Sum the Result - Total DC Power Exercises Case Study: AC Power Computation Build the Macro Occurrence Table Find the Number of Darlington Outputs Compute AC Power for all ECL Darlington Output Macros Find the Number of ECL Inputs Compute AM Power for all ECL Input Macros Find the Number of Internal Macros Compute AC Power for all Internal Macros Sum All Components of AC Power Total Power Dissipation Exercises Chapter 8 Simulation Case Study: Simulation Chapter 9 Faults and Fault Detection Chapter 10 Design Submission ASIC Glossary Glossary A-D Glossary E-K Glossary L-R Glossary S-Z Symbols	zdf SEFb ERb
Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises For problems or questions on these pages, contact dew@Donnamaie.com

by Donnamaie E. White