Logic Design for Array-Based Circuits


Logic Design for Array-Based Circuits by Donnamaie E. White Copyright © 1996, 2001, 2002 Donnamaie E. White

Table of Contents Preface Overview Chapter 1 Introduction Chapter 2 Structured Design Methodology Chapter 3 Sizing the Design Chapter 3 Appendix = Case Study in Sizing a Design Chapter 4 Design Optimization Chapter 5 Timing Analysis for Arrays Chapter 6 External Set-up and Hold Times Chapter 7 Power Considerations Case Study: DC Power Computation Case Study: AC Power Computation Chapter 8 Simulation Case Study: Simulation Chapter 9 Faults and Fault Detection Introduction Controllability Observability Masking a Fault Fault Types Fault Equivalencies Single Stuck-At Faults Minimal Test Sets Example Test Set The Problem Combinatorial Circuit Formation Rules for the Existence Function Forming Links Selecting a Chain Advantages of the Test Sequence Simple Gates - Sequences Extension to Three-State and Bidirectional Structures Extension to Sequential Circuits Reference Case Study - 16:1 MUX D Flip/Flop Circuit 100% Fault-Grade Vector Set The Marquand Map 2;1 MUX Example 3:1 MUX Example 16:1 MUX Actual Test Vectors Chapter 10 Design Submission ASIC Glossary Glossary A-D Glossary E-K Glossary L-R Glossary S-Z Symbols	zdf SEFb ERb
Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises For problems or questions on these pages, contact dew@Donnamaie.com