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VHDL Coding Styles and Methodologies, Second Edition
Author: Cohen, Ben

Cover: Hard cover
Pages: 453
List Price: $125.00
Published by Kluwers Academic Publishers
Date Published: 02/1999
ISBN: 0792384741


VHDL Coding Styles and Methodologies, 2nd Edition is a follow up book to the first edition of same book and to VHDL Answers to Frequently Asked Questions, first and second editions. This book was originally written as a teaching tool for a VHDL training course. The author began writing the book because he could not find a practical and easy to read book that gave in depth coverage of both, the language and coding methodologies. This edition provides practical information on reusable software methodologies for the design of bus functional models for testbenches. It also provides guidelines in the use of VHDL for synthesis. All VHDL code described in the book is on a companion CD. The CD also includes the GNU toolsuite with EMACS language sensitive editor (with VHDL, Verilog, and other language templates), and TSHELL tools that emulate a Unix shell. Model Technology graciously included a timed evaluation version of ModelSim, a recognized industry standard VHDL/Verilog compiler and simulator that supports easy viewing of the models under analysis, along with many debug features. In addition, Synplicity included a timed version of Synplify, a very efficient, user friendly and easy to use FPGA synthesis tool. Synplify provides a user both the RTL and gate level views of the synthesized model, and a performance report of the design. Optimization mechanisms are provided in the tool.

This book is intended for:

    1. College students. It is organized in thirteen chapters, each covering a separate aspect of the language, with complete examples. Students can compile and simulate the examples to get a greater understanding of the language. Each chapter includes a series of exercises to reinforce the concepts.

    2. Engineers. It is written by an aerospace engineer who has many years of hardware, software, computer architecture and simulation experience. It covers practical applications of VHDL with coding styles and methodologies that represent what is current in the industry. VHDL synthesizable constructs are identified. Included are practical guidelines for the design of bus functional models used in testbenches, such as waveform generation, client/server control, text and binary file command methods, and binary file generation schemes. Also included is an elaboration of a project for the design of a synthesizable Universal Asynchronous Receiver Transmitter (UART), and a testbench to verify proper operation of the UART in a realistic environment, with CPU interfaces and transmission line jitter. An introduction to VHDL Initiative Toward ASIC Libraries (VITAL) is also provided. The book emphasizes VHDL 1987 standard but provides guidelines for features implemented in VHDL 1993.

This book differs from other VHDL books in the following respects:

    1. Emphasizes VHDL core, Ada like sequential aspects and restrictions, along with the VHDL specific, concurrent aspects of the language.

    2. Uses complete examples with good code, and code with common mistakes experienced by users to demonstrate the language restrictions and misunderstandings.

    3. Provides a CD that includes all the book examples in addition to GNU EMACS language sensitive editor, other useful reference VHDL code material, and GNU TSHELL.

    4. Uses an easy to remember symbology notation throughout the book to emphasize language rules, good and poor methodology and coding styles.

    5. Identifies obsolete VHDL constructs to be avoided.

    6. Identifies non-synthesizable structures.

    7. Covers practical design of testbenches for modeling the environment and automatic verification of a unit under test.

    8. Provides a complete design example that uses the guidelines presented in the book.

    9. Provides an introduction to VITAL.

    10. Provides guidelines for synthesis and identifies the VHDL constructs that are typically synthesizable.

This book is organized in four basic VHDL aspects:

    1. SEQUENTIAL LANGUAGE. This is similar to the sequential aspects of other programming languages like C or Ada. Chapter 1 provides sufficient knowledge to compile and simulate a simple counter. Chapter 2 covers the basic language elements including the lexical elements, the syntax, and the types. Chapter 3 discusses the control structures.

    2. CONCURRENCY. This differentiates VHDL from other sequential languages. Chapter 4 discusses drivers, chapter 5 covers the timing and chapter 6 emphasizes the concurrent statements.

    3. ADVANCED TOPICS. This includes subprograms in chapter 7, packages in chapter 8, and attributes, specifications and configurations in chapter 9, and design for synthesis in chapter 10.

    4. APPLICATIONS. This emphasizes reusable software methods to generate functional models, bus functional models, and testbench designs in chapter 11; a UART project with synthesizable transmitter and receiver in a testbench environment in chapter 12; VITAL coding style optional methodology in chapter 13.

The language rules, coding styles, and methodologies presented in this book support the structure necessary to create digital hardware designs and models that are readable, maintainable, predictable, and efficient.