Tutorial I: The 15 Minute Design                 2  
      Design Entry using the Graphic Editor          6  
      Compiling the Design                           9  
      Simulation of the Design                       10 
      Downloading Your Design to the UP 1 Board      12 
      The 10 Minute VHDL Entry Tutorial              14 
      Compiling the VHDL Design                      17 
      The 10 Minute Verilog Entry Tutorial           17 
      Compiling the Verilog Design                   21 
      Timing Analysis                                22 
      The Floorplan Editor                           23 
      Symbols and Hierarchy                          24 
      Functional Simulation                          24 
      For additional information                     24 
      Laboratory Exercises                           25 
    The Altera UP 1 CPLD Board                       30 
      Programming Jumpers                            31 
      MAX 7000 Device and UP 1 I/O Features          31 
      MAX and FLEX Seven-segment LED Displays        31 
      FLEX 10K Device and UP 1 I/O Features          34 
      Obtaining a UP 1 Board and Power Supply        36 
    Programmable Logic Technology                    38 
      CPLDs and FPGAs                                40 
      Altera MAX 7000S Architecture -- A Product     41 
      Term CPLD Device
      Altera FLEX 10K Architecture -- A Look-Up      42 
      Table CPLD Device
      Xilinx 4000 Architecture -- A Look-Up Table    46 
      FPGA Device
      Computer Aided Design Tools for                48 
      Programmable Logic
      Applications of FPLDs                          48 
      For Additional Information                     49 
      Laboratory Exercises                           49 
    Tutorial II: Sequential Design and Hierarchy     52 
      Install the Tutorial Files and UP1 core        52 
      Library
      Open the Tutor2 Schematic                      52 
      Browse the Hierarchy                           54 
      Using Buses in a Schematic                     55 
      Testing the Pushbutton Counter and Displays    56 
      Testing the Initial Design on the UP 1         57 
      Board.
      Fixing the Switch Contact Bounce Problem       58 
      Testing the Modified Design on the UP 1        59 
      Board.
      Laboratory Exercises                           59 
    UP1core Library Functions                        64 
      UP1core DEC-7SEG: Hex to Seven-segment         65 
      Decoder
      UP1core Debounce: Pushbutton Debounce          66 
      UP1core OnePulse: Pushbutton Single Pulse      67 
      UP1core Clk_Div: Clock Divider                 68 
      UP1core VGA_Sync: VGA Video Sync Generation    69 
      UP1core CHAR_ROM: Character Generation ROM     71 
      UP1core Keyboard: Read Keyboard Scan Code      72 
      UP1core Mouse: Mouse Cursor                    73 
    Using VHDL for Synthesis of Digital Hardware     76 
      VHDL Data Types                                76 
      VHDL Operators                                 77 
      VHDL Based Synthesis of Digital Hardware       78 
      VHDL Synthesis Models of Gate Networks         78 
      VHDL Synthesis Model of a Seven-segment LED    79 
      Decoder
      VHDL Synthesis Model of a Multiplexer          81 
      VHDL Synthesis Model of Tri-State Output       82 
      VHDL Synthesis Models of Flip-flops and        82 
      Registers
      Accidental Synthesis of Inferred Latches       84 
      VHDL Synthesis Model of a Counter              84 
      VHDL Synthesis Model of a State Machine        85 
      VHDL Synthesis Model of an ALU with an         87 
      Adder/Subtractor and a Shifter
      VHDL Synthesis of Multiply and Divide          88 
      Hardware
      VHDL Synthesis Models for Memory               89 
      Hierarchy in VHDL Synthesis Models             92 
      Using a Testbench for Verification             94 
      For Additional Information                     95 
      Laboratory Exercises                           95 
    State Machine Design: The Electric Train         100
    Controller
      The Train Control Problem                      100
      Track Power (T1,T2,T3, and T4)                 102
      Track Direction (DA1-DA0, and DB1-DB0)         102
      Switch Direction (SW1,SW2, and SW3)            103
      Train Sensor Input Signals (S1,S2,S3,S4,and    103
      S5)
      An Example Controller Design                   104
      VHDL Based Example Controller Design           108
      Simulation Vector File for State Machine       110
      Simulation
      Running the Train Control Simulation           113
      Running the Video Train System (After          114
      Successful Simulation)
      Laboratory Exercises                           115
    A Simple Computer Design: The μP 1            120
      Computer Programs and Instructions             121
      The Processor Fetch, Decode and Execute        122
      Cycle
      VHDL Model of the μP 1                      126
      Simulation of the μP 1 Computer             129
      Laboratory Exercises                           130
    VGA Video Display Generation                     134
      Video Display Technology                       134
      Video Refresh                                  134
      Using a CPLD for VGA Video Signal Generation   137
      A VHDL Sync Generation Example: UP1core        138
      VGA_SYNC
      Final Output Register for Video Signals        140
      Required Pin Assignments for Video Output      140
      Video Examples                                 141
      A Character Based Video Design                 141
      Character Selection and Fonts                  142
      VHDL Character Display Design Examples         145
      A Graphics memory design example               147
      Video Data Compression                         148
      Video Color Mixing using Dithering             149
      VHDL Graphics Display Design Example           149
      Laboratory Exercises                           151
    Communications: Interfacing to the PS/2          154
    Keyboard
      PS/2 Port Connections                          154
      Keyboard Scan Codes                            155
      Make and Break Codes                           155
      The PS/2 Serial Data Transmission Protocol     155
      Scan Code Set 2 for the PS/2 Keyboard          158
      The Keyboard UP1core                           160
      A design example using the Keyboard UP1core    163
      For additional information                     164
      Laboratory Exercises                           164
    Communications: Interfacing to the PS/2 Mouse    166
      The Mouse UP1core                              168
      Mouse Initialization                           168
      Mouse Data Packet Processing                   169
      An example design using the Mouse UP1core      170
      For additional information                     170
      Laboratory Exercises                           170
    Robotics: The UP1-bot                            172
      The UP1-bot Design                             172
      UP1-bot Servo Drive Motors                     172
      Modifying the Servos to make Drive Motors      173
      VHDL Servo Driver Code for the UP1-bot         174
      Sensors for the UP1-bot                        176
      Assembly of the UP1-bot Body                   181
      UP1-bot FLEX Expansion B Header Pins           188
      For Additional Information                     189
      Laboratory Exercises                           190
    A RISC Design: Synthesis of the MIPS             196
    Processor Core
      The MIPS Instruction Set and Processor         196
      Using VHDL to Synthesize the MIPS Processor    199
      Core
      The Top Level Module                           200
      The Control Unit                               203
      The Instruction Fetch Stage                    205
      The Decode Stage                               208
      The Execute Stage                              210
      The Data Memory Stage                          212
      Simulation of the MIPS Design                  213
      MIPS Hardware Implementation on the UP 1       214
      Board
      For Additional Information                     215
      Laboratory Exercises                           216
  Appendix A: Generation of Pseudo Random Binary     221
  Sequences
  Appendix B: MAX+PLUS II Design and Data File       223
  Extensions
  Appendix C: UP 1 Pin Assignments                   225
  Glossary                                           228
  Index                                              237
  About the Accompanying CD-ROM                      240