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Perfect 437 Pages Published by Verification Central Date Published: 08/2001 ISBN: 097119940X

Summary
The Art of Verification with Vera covers the essential elements of VERA with detailed examples demonstrating how the VERA testbench tool and the OpenVera language can be harnessed to effectively verify different types of designs. It helps the reader understand critical verification issues and teaches how to expedite and enhance functional design verification.

This book discusses a range of verification issues including test case identification, stimulus generation, results checking, test coverage and test regression. Theses concepts are used to develop a verification strategy and a VERA testbench for a common design. Each component of this testbench is discussed in detail to demonstrate the methodologies presented.

Highlights include:

• Comprehensive discussion of verification strategies for complex System-on-a-chip designs.
• Identifying test cases and testbench components Strategies for stimulus generation
• Monitors and result-checking strategies
• How to Build complex testbenches with Vera
• Using Veras classes to do automatic stimulus generators, transactors and monitors
• Run-time constraints with Vera
• A detailed testbench for the Ethernet MAC
• Practical issues in ASIC Verification
• Test space coverage versus code coverage vDebugging strategies
• Regressions