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Portions from Application-Specific Integrated Circuits Copyright © 1997 by Addison Wesley Longman, Inc.Figure 2.11 defines the design rules for a CMOS process using pictures. Arrows between objects denote a minimum spacing, and arrows showing the size of an object denote a minimum width. Rule 3.1, for example, is the minimum width of poly (2 l ). Each of the rule numbers may have different values for different manufacturers—there are no standards for design rules. Tables 2.7–2.9 show the MOSIS scalable CMOS rules. Table 2.7 shows the layer rules for the process front end , which is the front end of the line (as in production line) or FEOL . Table 2.8 shows the rules for the process back end ( BEOL ), the metal interconnect, and Table 2.9 shows the rules for the pad layer and glass layer.
FIGURE 2.11 The MOSIS scalable CMOS design rules (rev. 7). Dimensions are in l . Rule numbers are in parentheses (missing rule sets 11–13 are extensions to this basic process). |
TABLE 2.7 MOSIS scalable CMOS rules version 7—the process front end. |
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minimum select spacing to channel of transistor 1 |
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minimum select width and spacing 2 |
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TABLE 2.8 MOSIS scalable CMOS rules version 7—the process back end. |
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TABLE 2.9 MOSIS scalable CMOS rules version 7—the pads and overglass (passivation). |
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The rules in Table 2.7 and Table 2.8 are given as multiples of l . If we use lambda-based rules we can move between successive process generations just by changing the value of l . For example, we can scale 0.5 m m layouts ( l = 0.25 m m) by a factor of 0.175 / 0.25 for a 0.35 m m process ( l = 0.175 m m)—at least in theory. You may get an inkling of the practical problems from the fact that the values for pad dimensions and spacing in Table 2.9 are given in microns and not in l . This is because bonding to the pads is an operation that does not scale well. Often companies have two sets of design rules: one in l (with fractional l rules) and the other in microns. Ideally we would like to express all of the design rules in integer multiples of l . This was true for revisions 4–6, but not revision 7 of the MOSIS rules. In revision 7 rules 5.2a/6.2a are noninteger. The original Mead–Conway NMOS rules include a noninteger 1.5 l rule for the implant layer.
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