Bit-Slice Design: Controllers and ALUs

by Donnamaie E. White

Copyright © 1996, 2001, 2002 Donnamaie E. White



Table of Contents

1. Introduction

2. Simple Controllers

3. Adding Programming Support to the Controller

4. Refining the CCU

5. Evolution of the ALU

6. The ALU and Basic Arithmetic

7. Tying the System Together




Simple Controller continued

Last Edit October 10, 1996; May 1, 1999; July 9, 2001

Conditional Branch

It is sometimes desireable to terminate a microroutine in one of several different ways depending on one or more conditions. For example, the conditions tested could be the various status bit outputs of the ALU based on the result of an operation. Status outputs can include

  1. Z=1 if ACC=0
  2. S=1 if ACC < 0
  3. Cout=1 if | ACC | > range
  4. OVR (overflow)=1 if error
  5. on the result of a compare operation
Only one condition is testable at a time. Hardware could be used to combine a number of conditions to supply one test bit if that combination is expected to occur frequently. A program Flow diagram for a conditional branch is shown in Figure 2-12.

Figure 2-12 Conditional Branch Flow Diagram. "IF-THEN-ELSE" - the conditional branch (CJP, conditional jump)

microcode diagram showing flow of  conditional JMP  sequences

The ability to test a condition and to branch if the condition is TRUE is provided by adding a MUX at the counter load control. The load control filed in the microword is changed to a branch condition select, which selects

  1. ground (count; no branch)
  2. condition 1 or condition 2 (load branch address into counter if TRUE)
  3. Vcc (unconditional branch, load counter).
The CCU is shown in Figure 2-13, with its microword format shown in Figure 2-14.

Figure 2-13 CCU with Conditional Branch Capability

simple block diagram with counter load control MUX added and microword expanded to include branch condition select

Figure 2-14 Microword Format for Conditional Branch (A) Detail of Load Control MUX

load control MUX detail

Figure 2-14 Microword Format for Conditional Branch (B) Detail of Microword Format

Load, EN
Op Code
o o o
2 bits 1 bit n bits 4-6 bits 2 bits 1 bit 1-4 bits 1-4 bits

A sample piece of microcode is shown in Figure 2-15 that has both unconditional and conditional branches. As with most programming languages, if a conditional test fails (FALSE), execution continues sequentially, as shown in statements at addresses 30 and 31. The branch condition select field is 2 bits wide in this example. A wider field would allow a larger MUX and threrfore would allow more conditions to be tested.

Figure 2-15 Microcode, Demonstrating Conditional Jumps

microcode written to show conditional JMP  sequences






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Copyright © September 1996, 1999, 2001, 2002 Donnamaie E. White White Enterprises