Bit-Slice Design: Controllers and ALUs

Refining the CCU

Last Edit November 2, 1996; May 1, 1999; July 7, 2001

Am2910 Instructions

Table 4-1 Effect of CCEN = HIGH (CCEN is a complemented pin)

1. Jump Zero (JZ)

   Jump to Zero: Power-up or restart sequences need to use the Jump Zero instruction if the stack is to be used anywhere in the microprogram. JZ resets the TOS pointer to binary 0. JZ may be made to execute in various ways.

   If a pipeline is being used, resetting the pipeline register to all zero sends 0₁₆ as the hex code for the instruction word. Since 0₁₆ = JZ (0000), the Am2910 executes JZ. A reset, restart or power-up control should cause the pipeline to reset.
   
   Where the pipeline on the PROM memory does not exist, the OE' control on the Am2910 can be used with 10K pull-up resistors to force FFF₁₆ on the address lines into the PROM memory. The JZ instruction should be placed at this location. This approach requires and extra microword in the memory, which is not usually a problem. Either of these appraoches is satisfactory.
   
   JZ does not alter the register/counter, which is assumed to be undefined until reset. Any reference to the register/counter prior to a load instruction will result in unpredictable behavior.
   
   The pipeline is left enabled in this instruction. With the exceptions of instructions JMAP and CJV, the pipeline is left enabled to improve execution speeds. A flow diagram for JZ is shown in Figure 4-9.

1. Figure 4-9 Jump zero (JZ, 0, 0000)

   
   
   All instructions pass the next-address select bits, which include the Am2910 instruction field, the condition code multiplexer select bits, and any additional control pin fields (RLD', CCEN'). All instructions cause a next-address value to be switched through the next-address multiplexer and to be incremented by the incrementer.

2. Continue (CONT)

   Sequential Execution: Sequentional program segments use the Continue statement, whose flow is shown in Figure 4-10. The µPC register is the source of the next-address. The register/counter and the stack are not altered. The CC' input is unused. The pipeline output enable PL' is enabled.

   Figure 4-10 Continue (CONT, E, 1110)

   

3. Jump Map (JMAP)

   Jump to the Map address: JMAP is trhe instruction used to start different microroutines based on opcode decode, and a mapping PROM or the equivalent construct. This GO TO branches to the address appearing at the D_i inputs, and the MAP' output enable is active. In a CCU such as the one being discussed, this will gate the address output by the mapping PROM into the Am2910. The register/counter and stack are not affected. This statement is normally placed at the end of a microroutine or placed at a case-branch (jump-op) location in the microprogram (seeFigure 4-11).

   Figure 4-11 Jump map (JMAP, 2, 0010)

   

4. Conditional Jump PL (CJP)

   Jump to Pipeline Address If Condition is True Else Continue: The simplest IF construct used to test for the occurrence of an interrupt request is Conditional Jump to an address in the pipeline register. If the CC' input is LOW (the condition is TRUE), the next address is provided by the pipeline register. If the CC' is HIGH, the test fails and CJP behaves as CONT instruction. The pipeline is enabled and the stack and register/counter are unaffected (see Figure 4-12).

   Figure 4-12 Conditional jump pipeline (CJP, 3, 0011)

   

5. Conditional Jump Vector (CJV)

   Jump to Vector Map Address If Condition is True Else Continue: Another IF construct used to test for the occurrence of an interrupt request is Conditional Jump Vector. If the CC' input is LOW, the next address is provided by the vector map. The stack and register counter are unaffected. The VECT enable is ACTIVE. If CC' is HIGH, CJV behaves as CONT (see Figure 4-13).

   Figure 4-13 Conditional jump vector (CJV, 6, 0110)

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6. Load Counter and Continue (LDCT)

   There are several instructions which use the counter capability and several which use the register capability of the register/counter. Each requires that the register/counter be loaded prior to its execution. Load Counter and Continue provides this ability.

   LDCT behaves as a continue statement except that whatever is gated onto the D_i inputs is unconditionally loaded in the register/counter. The PL' enable is ACITVE; the stack is unaffected (see Figure 4-14).

   Figure 4-14 Load counter and continue (LDCT, C, 1100). This instruction must be executed before a LOOP instruction or a jump which used the register.

   

7. COND Jump R/PL (JRP)

   This should have been given the mnemonic CJRP since it is a conditional statement. (The mnemonic names refer to the Development System, AmSYS 29, preprogrammed Definition File.) The choice of where the next address comes from is made based on the CC' input. If CC' is LOW, the next address is from the piepline register. If CC' is HIGH, the next address is from the register/counter. LDCT must have occurred anywhere prior to the execution of JRP.

   Regardless of the test results, the flow is nonsequential. A branch is taken to one address or another.The PL' enable is ACTIVE, and the register/counter and the stack are unaffected (see Figure 4-15).

   Figure 4-15 Conditional jump register/pipeline (JRP, 7, 0111).
   LDCT must have been executed somewhere ahead of JRP.

   

8. COND JSB PL (CJS)

   Microprogram subroutines may be called by the Conditional Jump Subroutine, with the address of the first microinstruction of the subroutine given in the pipeline register. IF CC' is LOW, a branch is taken to the subroutine. The contents of the µPC, on which the flow diagram of Figure 4-16 is address 53, are pushed onto the stack and the TOS pointer is incremented. If CC' is HIGH, CJS behaves as CONT. The PL' enable is ACITVE; the stack is unaffected.

   Figure 4-16 Conditional jump subroutine from pipeline (CJS, 1, 0001)

   

9. COND JSB R/PL (JSRP)

   Subroutines may also be called by the Conditional Jump Subroutine from Register or Pipeline, which should have been given the mnemonic CSRP. The instruction is similar to JRP except that regardless of the test result, the next sequential address (54 in Figure 4-17) is pushed onto the stack and the TOS pointer is incremented. As with JRP, LDCT (or its equivalent operation) must have occurred prior to the execution of JSRP.
   

   Figure 4-17 Conditional jump subroutine register/pipeline (JSRP, 5, 0101).
   LDCT or a register load must occur somewhere prior to JSRP

   

   If CC' is LOW, a branch is taken to the subroutine whose address is taken from the register/counter (70 in the figure). The PL' enable is ACTIVE, and the register/counter and the stack are unaffected. If CC' is HIGH, the start address is taken from the branch address field (80 in the figure).

10. COND Return (CRTN)

    Once a subroutine has been completed, an unconditional return to the calling program is accomplished using a Conditional Return Statement. The same statement is also used to conditionally end a subroutine based on the result of a test.

    There are two ways to allow an unconditional return -- either the selcted input to the conditional MUX is a forced PASS input (grounded in the active-LOW case), or the CCEN' input is switched HIGH. CCEN' will be discussed later. If CC' is LOW either as a result of a valid test or frm a forced LOW input, the next address is taken from the LIFO stack and the stack is POPed (the TOS pointer is decremented). The register/counter is unaffected, and the PL' enable is ACTIVE.

    If CC' is HIGH, CRTN behaves as CONT. In either case, CRTN should not be executed if the stack is empty (see Figure 4-18).

    Figure 4-18 Conditional Return (CRTN, A, 1010)

    

11. Repeat PL CNTR <> 0 (RPCT)

    Loops are handled with four different instructions. One of these is RPCT, the Repeat Loop instruction, with the start address of the loop in the pipeline register. Essentially, it is a conditional jump pipeline instruction. The register/counter must have been loaded previously via a LDCT or equivalent operation.
    
    If the counter is not equal to 0 (zero), the jump is taken and the counter is decremented. If <COUNTER> = 0, then RPCT behaves as CONT. The stack is unaffected, and the PL' enable is active (see Figure 4-19).

    Figure 4-19 Repeat pipeline if counter <> 0 (RPCT, 9, 1001). (Loop on one or more statements, beginning address of loop in register (at the time of the RPCT statement).

    

12. Push/COND LD CNTR (PUSH)

    The counter can be conditionally loaded during the same instruction that pushes the current value of the µPC register onto the LIFO stack. If CC' is LOW, the counter is loaded from the pipeline register. If CC' is HIGH. the register/counter is unchanged. The PUSH occurs regardless of the CC' input value. The PL enable is active (see Figure 4-20).
    
    PUSH must immediately precede the first microinstruction in a loop controlled by LOOP, RFCT, or TWB.
    
    Figure 4-20 Push stack and condition load counter (PUSH, 4, 1000). This instruction must immediately precede the first statement in a loop controlled by LOOP or RFCT.

    

13. Repeat Loop, CNTR <> 0 (RFCT)

    Another Repeat Loop structure is RFCT, which causes a loop to be repeated if <COUNTER> <> 0. The start address of the loop is on the start of the stack. The counter is decremented when the branch is taken. If <COUNTER> = 0, RFCT behaves similarly to CONT with the added operation of POPping the stack. The PL' enable is active. A loop using RFCT requires PUSH immediately preceding the first microinstruction of the loop, the microinstruction whose address is to be pushed onto the stack (see Figure 4-21).
    
    Figure 4-21 Repeat loop from stack if counter &NE; 0 (RFCT, 8, 1000)

    

    RPCT and RFCT are both microprogramming equivalents of DO loops.

14. Test End Loop (LOOP)

    A third repeat loop construct is LOOP, which behaves similarly to RFCT except that the test which determines whether or not the loop is repeated is some selected condition other than <COUNTER> = 0. On CC' = HIGH, LOOP behaves similarly to CONT, with the added operation of POPping the stack. On CC' = LOW, the loop start address is referenced from the top of the stack. The register/counter is unaffected. The PL' enable is ACTIVE.

    A loop using the instruction LOOP requires that a PUSH instruction immediately preceed the first microinstruction in the loop, the one whose address is to be pushed onto the stack (see Figure 4-22).

    Figure 4-22 Test end of loop (LOOP, D, 1101). Must preceed first statement in the loop.

    

    The LOOP microinstruction is the programming equivalent of a DO UNTIL or DO WHILE programming construct.

15. COND JUMP PL and POP [stack] (CJPP)

    The way to conditionally exit a loop is to execute CJPP. This instruction may also be used to conditionally exit a subroutine where a return to the calling location is to be aborted.

    CJPP is a conditional jump using the pipeline register to provide the branch address (see Figure 4-23). The difference between CJP and CJPP is that the latter POPs the stack when CC' = LOW. When CC' = HIGH, CJPP becomes CONT. The PL' enable is ACTIVE.

    Figure 4-23 Conditional jump pipeline and POP (CJPP, B, 1011)

    

    CJPP is used to conditionally exit loops formed using PUSH and RFCT, TWB or LOOP. It is not needed for loops formed with RPCT which do not invlove the stack.

16. Three-Way Branch (TWB)

    There can be instances where the construct DO X TIMES WHILE C_i = FALSE is necessary. The microinstruction equivalent of this is TWB, a dual-test branch or loop microinstruction (see Figure 4-24).
    
    TWB will loop, referring to the top of the stack for the start adress, if CC' = HIGH and <COUNTER> <> 0. The stack wil be POPped on the branch if CC' = HIGH and <COUNTER> = 0. TWB will behave similarly to CONT if CC' = LOW with the addition of POPping the stack, regardless of the counter value. If <COUNTER> <>0, the counter will be decremented. In all cases, the PL' enable is active.
    
    Figure 4-24 Three-way branch (TWB, F, 1111)

    

    An example of the type of problem for which TWB is useful is given in Figure 4-25. This is a key match memory search, where the counter defines the length of the block of memory being searched and the condition tested is a match on the selected key.
    
    Figure 4-25 Programming a memory search on key for a search on n+1 locations