There are many benefits from very small, minimal physical layout dimensions in VLSI chips, but they come at a very high price. The cost of the latest technology in semiconductor processing lines is going through the roof. There are many consequences of such costly lines. First and foremost, once in use, these lines should never be idle. Running or not running, they cost millions a day and they function better if running continuously. However, it is obviously difficult to fill these lines with new designs, when it takes years of design to finish a new, high-complexity chip. In addition, with the increase in yield and wafer size, the number of chips coming off a single wafer is growing enormously, while the wafer count is accordingly decreasing. It takes a very large demand for chips to keep the fabrication sites running continuously.

Clearly, shortening the design cycle through Hard and Soft IP reuse is one way to address this problem.

One of the most astonishing feats in the field of hi-tech chip production is the relentless progress made in processing technologies. The smallest feasible physical dimensions keep getting smaller with no end in sight, and the chips still work. This may come as a surprise to some who have spent years studying semiconductor physics in depth. It does to the author. It would be expected that by now at least some of the “fundamental” physical limits might have resulted in some “interesting,” potentially “deadly” effects beyond just the dominance of interconnects for timing. Of course, many extremely challenging effects appear all the time but, apparently, clever engineers always seem to find ways around them without major disruptions.

As a direct consequence of DSM technology, it can be said that understanding many more details of physics matters again, not only for processing today's VLSI digital circuits but also for designing them. An increasing number of intricate details needs to be taken into account when designing and processing these chips. However, aside from the timing closure problems caused by interconnect delays, the dominant factors are not so much related to how the semiconductor devices function as layout dimensions get smaller. Some of the more important factors presently seem related to yield, some of which can be addressed directly through the use of compaction techniques. We discuss yield improvements through flexible layout rules in Chapter 5. However, we will focus on rules related to layout issues, because they can be elegantly addressed with compaction. Physical layout and design rule manipulations for yield improvements fall under the relatively new term of Design for Manufacturing (DfM). It is a topic that is currently generating a lot of interest.


A nontechnical factor that makes it difficult to anticipate profitability, the level of activity of the processing line and justification of heavy investments is the potential state of the economy at the time the processing line is put into service.

Today, a large percentage of the chips are used in consumer electronics. It is a large volume market, which, as such, is good. The military market used to act somewhat as a buffer against fluctuations in the economy for this hi-tech industry, when military, highly priced, high-quality parts helped profit margins. However, this was before enormous volumes of chips were being produced, as is the case today. Because of this strong dependency on consumers who are willing to spend money on gadgets they do not absolutely need, the chip industry is extremely vulnerable to economic ups and downs.

For an industry that is as capital-intensive as the chip manufacturing industry, the economics of reality is hard to deal with. Without any buffers, the industry is held hostage by the whims of the consumer market and its fickle supply and demand. Large expenditures for new fabrication site construction is a very high risk to take. Of course, it is well known that not taking large risks in hi-tech is just as disastrous.

Long-range planning in the chip industry is extremely difficult and painful. Japan is a good example of how difficult it is to predict the economy. Until recently, it was thought that a country such as Japan would never experience a prolonged recession. Well, we all know better now.

So, what to do? Again, as we will see, especially Hard IP reuse with its shortened reuse cycle makes chips available faster for processing. It shortens the planning cycle. This will help a lot to fill fabrication sites. But, it also gives a lot of flexibility to companies without fabrication sites by allowing them to change from one process to another very quickly. Just resubmit a compaction run with different process parameters and the chip is ready to he processed by another foundry. This flexibility for the company without a fabrication site also lightens the burden of scheduling “the right amount” of fabrication capacity. After all, it sometimes happens that the commercial success of a design far exceeds expectations.

Can Hard IP reuse help if a foundry suddenly experiences yield problems? Or worse, what if your foundry of choice is hit by calamity? The flexibility afforded by Hard IP reuse lightens this worry, but it also creates a very tough and competitive environment for the foundries.

Finally, as will become clear later, once a chips is set up for migration, changes in your favorite foundry's process rules, due to adjustments that help improve yield, are not a serious problem for chips that have already been laid out. A few computer runs and a new layout that benefits from the “new, improved” layout rules becomes available for processing. We also show in Chapter 2 that feedback from migration runs may suggest such yield or performance enhancing adjustments in the technology file that contains the process parameters.


Now that we have discussed many of the challenges of designing DSM VLSI chips productively and with optimum performance, we will preview some areas of application for IP reuse, IP creation, IP optimization and fabrication yield enhancements via physical layout manipulations. To describe these approaches, we suggest the term Hard IP engineering. In the following chapters, we discuss these applications in more detail.


The databases describing the physical layout, the Hard IP, can he in one of several formats. These databases contain at least the information necessary to eventually produce masks for fabricating chips. This data describes the position of every polygon edge on the physical layout of a chip. If none of the placements of the polygon edges violates any of the processing design rules (minimum metal widths, minimum distance between metal lines, minimum size of contact openings, etc.), the layout contains no layout design rule errors and is design rule correct (DRC). These rules enable the silicon to be fabricated successfully with an acceptable percentage of good chips (yield) on a processed wafer from the processing point of view.

We should realize that these rules have never been cast in concrete. In situations where design engineers and processing engineers have worked hand-in-hand, these layout rules have always been “negotiable” for pre-DSM technologies and even much more so for the present DSM technologies. However, with the current increasing challenges of ultrasmall layout dimensions, the great number of devices per chips, the large size of wafers and chips and the extreme need for competitiveness, DfM has become a very important issue. Fortunately, compaction methodology lends a hand in determining the best trade-offs.

While we address these issues in some detail in Chapters 2 and 5, we will just briefly describe the general idea of DfM. Going from an existing to a more aggressive process, it does not make sense to reduce all or perhaps even most of the layout dimensions to the smallest values allowed by the new process. Sonic layout dimensions affect the performance of a circuit much less than others. If these dimensions are laid out unnecessarily small, it will just result in a waste of manufacturing yield. On the other hand, some of them may increase the size of the layout. For DSM technologies, truly intelligent trade-offs between reducing layout dimensions selectively to gain speed performance without reducing manufacturing yield or paying a serious price in chip size have become a commonly discussed issue in DfM.

In addition to the processing-related layout design rules, there are rules concerning electrical and reliability issues. The source of concern is not just the fabrication of a chip. We have already mentioned electromigration and keeping the resistance of interconnects within acceptable limits. We have suggested that certain interconnects need a minimum distance between them to restrict capacitive cross-coupling to acceptable limits. They may need to be balanced to maintain the time skew between certain signals within specified limits. There are normally many more such specifications. These inputs are user controls specified by layout specialists and circuit designers with the aid of analysis tools and other data.