So far, wc have discussed placing (integrating) a number of chips or blocks known to work that may have been fabricated with a variety of technologies on one chip so that they can be produced using the latest processing technology. This, of course, is an interesting challenge. In fact, aside from some serious technical challenges, this S-o-C scenario offers rather interesting possibilities.

The level of potential integration can range from mixing and matching not only digital Hard IP components but including digital and analog components on the same chip. Although far from trivial, this has been done and, in fact, is now being done routinely by some companies. It is discussed in Chapter 5. Another possibility is the mixing and matching of Soft IP and Hard IP on the same chip. It seems that this approach is still more in the planning stage than an actuality at this time.

Although some of these IP reuse applications for S-o-C may seem a bit futuristic, projects using these approaches have already been carried out. In general, feasibility is not the question. The actual challenges depend very much on the particular project. Later, we will attempt to list some guidelines related to the major difficulties and examine how it may be possible to overcome them.

So far, we have talked mostly about how to reuse or optimize existing IP. Compaction in conjunction with physical layout also allows a very productive and painless layout or Hard IP creation. We discuss this in Chapter 4.

Many discussions about IP reuse prompt questions about whether IP reuse offers significant relief in major areas of concern, where IP reuse makes sense and where it does not.

A careful analysis of available resources, time-to-market requirements, obsolescence of circuit or chip design and the risks of a completely new design is required to choose between Hard IP reuse and design from scratch and Soft IP reuse. Such objectivity is a real challenge for management and engineers.

Engineers always know ways to “improve” a circuit no matter how well it works. Engineers literally hate engineering “warm ups.” An engineer's top priority is to create the most elegant solution that offers the highest possible performance. And, engineers almost always underestimate the efforts required. They tend to be too optimistic about what is possible.

On the other hand, management generally leans towards issues such as minimizing cost, minimizing or guaranteeing the time-to-market with a performance that is “good enough.” However, because good engineers are hard to find, it is often better to keep them happy and let them do some creative design work from scratch. In periods when the demand for higher performance chips is greatest, suggesting an emphasis on reuse, engineering talent is also in insufficient supply. This is a real dilemma, and it is difficult to find the best objective compromise.

So who wins? Most of the time design from scratch and Soft IP win, unless time pressure is simply too great. Besides, there is also a compromise solution for the design of an entire system. At least some circuits can be migrated for reuse, others will be redesigned.

There is another possibility for keeping a balance: Let the engineers be creative and the computers do the Hard IP migration. IP creation itself requires creativity, but not polygon pushing or DRC fixing.

In all fairness, because progress in processing technology is so incredibly rapid, the time span between newer, more aggressive processes is so short that obsolescence in the design philosophy used for reusable IP often has not had time to become a major issue.

Today, synthesis and Soft IP based design methodologies are well established in the EDA industry and the associated skills are extremely marketable. Hard IP migration requires a different set of skills that address only a niche market. Besides, although Hard IP reuse provides undeniable benefits in many situations, being good at Hard IP migration requires a respectable level of skill and dedication.

At present, finding engineers and managers willing to commit their talent to Hard IP migration is still difficult. The infrastructure in design companies does not adequately support Hard IP migration. This will undoubtedly change with time.

Finally, one of the top priorities for Hard IP migration software providers will have to be to become integrated seamlessly into Soft IP and the design environment to minimize the threshold between any of the various design or reuse approaches.

It has to be painless to switch between the various paths leading to a higher performance chip!

Clearly, Hard IP reuse has its limitations. The design to be reused has to be taken more or less as it is. If the gap between the old process and the new process is too large, it may not make sense to migrate. If the number of metal layers from source to target process changes, migration can not take full advantage of the change. If the floorplan of the source chip is not acceptable, it can not be changed except in the S-o-C scenario. If the aspect ratios of the source blocks are not acceptable, they can not be changed for the target design.

Minimizing the risks, the time-to-market, engineering resources and very expensive verification tools does have a price!

However, a rapid retargeting, an adjustment to changing process-induced layout rules, an optimization of chip timing or the need to reuse the painfully developed software that is part of a VLSI system may make a Hard IP reuse approach well worth considering.

To justify any new design methodology, it has to be technologically sound and, in today's stock market driven economy, it has to bring about higher productivity and savings in terms of the time-to-market and investments of expensive resources, such as highly skilled engineering and expensive design tools.

We will in the following chapters attempt to show compaction as a useful approach in different areas, and we will discuss them as follows:

1. We show how to use compaction on Hard IP through retargeting of existing, previously used, designs in Chapters 2 and 7. In Chapter 2, wc demonstrate a well established retargeting methodology to gain an understanding of what is involved in such a retargeting approach. In Chapter 7, we compare a Hard IP retargeting flow with more classical approaches to designing chips from scratch and Soft IP reuse.
2. We show how to use compaction to optimize chip layouts in Chapter 3. This will demonstrate a strong complementary value to any of the design methodologies be it synthesis-based, standard cell-based or fully custom.
3. We show how compaction provides a methodology for very productive IP creation in Chapter 4.
4. We show how useful compaction is in trading off certain minimum layout dimensions, increasing manufacturing yield without sacrificing performance, based on DfM principles discussed in Chapter 5
5. Finally, we show how to use compaction to streamline the S-o-C approach in Chapter 5 by reusing some of the designs placed on the S-o-C. We propose a hybrid approach by integrating and retargeting Hard IP, Soft IP and other designs and saving valuable engineering time.