If a layout to be retargeted has 45 degree layout features, it often represents something of a challenge. One challenge is that some foundries do not accept 45 degree features. The other one is more migration complexity. It is not sufficient to just be able to compact 45 degree layout features, as Figure 2.13 indicates. Just performing a 45 degree compaction would waste area as shown in tire center of Figure 2,13. The 45 degree layout feature also needs to be elongated. This is perfectly possible for compaction. As an alternative, it might be desirable to convert 45 degree layout features to 90 degrees or to staircases.

Fig. 2.13 Forty Five Degrees are no Problem for Compaction

Actually, 45 degree layout features often present some additional challenges like, for example, two 45 degree layers crossing at 90 degrees. However, some of these challenges illustrate an important point about compaction. The compactor can be taught new tricks.

Looking at all the layout features that could ever occur, it should not be surprising that new geometries never seen before could appear. In fact, they do. As previously mentioned, completely new layout rules could appear with some of the latest technologies, or just a very strange layout geometry. Such new situations may require some setup modifications. The flexibility inherent in compaction allows such modifications. Yes, it will be reflected in a longer setup time before compaction can be initially run. However, as already suggested, once set up, reruns of the compaction of a chip to adjust for process parameter changes will be just computer time. This large flexibility enables solutions for even the “strangest” layouts.


We have discussed some of the typical challenges and capabilities of compaction. Since this book is neither a catalogue nor a manual, many of the additional possibilities and capabilities of compaction have not been discussed. In many ways, every compaction project has it own special idiosyncrasies, most of which an experienced operator can overcome. Fortunately, many projects are straightforward.

Hard IP reuse through compaction, saves a lot of time and investment in tools and engineering talent and is a very useful approach to IP reuse. The key is to judge intelligently when Hard IP reuse is the most beneficial approach. I believe that with growing awareness and experience with Hard IP reuse, it will be judged the best solution more and more often.


Compaction, which is the heart of modern Hard IP migration, began in silicon compilation when compaction was one way to achieve foundry independence and portability. A few years ago it became obvious that compaction could stand on its own as a methodology. It became clear that the semiconductor processing technology was moving at such a rapid pace that design methodologies could not produce new designs fast enough to keep up. Progress in semiconductor processing is happening due to many contributing factors, such as lithography, electron beam technology applications, new etching techniques and advancement in materials used.

Since the chips in use were perfectly good except that their physical layout was based on outdated processes, linear shrink and, lately, compaction started to look attractive for quickly taking advantage of the rapid advances in processing capability. Hard IP retargeting to IP reuse was born.

Of course, a lot of development work was needed to move from having a compaction engine packaged somewhere in silicon compilation software to creating a complete, standalone Hard IP migration environment. Then, there was and remains the challenge to continuously improve compaction algorithms to be able to keep up with the rapid progress in semiconductor processing technology and the resulting, immense increase in device counts on chips. Of course, as for all other hi-tech design methodologies, this continued learning process is a must for staying in business. We will now review the evolution of the compaction methodology over recent years and assess its present status and where it is going.

We will now look at some of the possible applications of Hard IP migration. Clearly, like with any evolution, we start with the easiest, early applications and move towards more difficult, present and future projects. We will first discuss library migration, an application area has been possible for quite some time now and one that is still very important today. We will then move towards the migration of bigger blocks, such as memories, data paths, and eventually entire chips. Clearly, the rapidly increasing size and complexity of today's chips is one of the major difficulties to face.

Increasing chip complexity will force us to very quickly address one of the major issues in the migration of complex layouts, maintenance of the hierarchy of source layout through the migration process. We will see that hierarchy in layout is quite a different concept from that of hierarchy as normally discussed in design methodologies, where top-down and bottom-up and “high-level” for functional or behavior-level design versus “low-level” for a transistor-level design are considered.

We will introduce the concept of hierarchy maintenance in layouts for regular structures in Section 2.5.2, the difficulty of maintaining hierarchy for complex layout structures in Section 2.5.3 and the limited hierarchy maintenance for complete chips in Section 2.4.5, based on today's and yesterday's compaction engines. Finally, in Chapter 5, we discuss unlimited hierarchy maintenance that is currently becoming available with the latest compaction technologies.


Compaction is compute-intensive and the first projects in retargeting were standard cell libraries. This area of application was an obvious one, since libraries used in synthesis were becoming obsolete as fast as processing capability was advancing. Figure 2.14 graphically shows a standard cell migration.

Just two years ago, library migration was a challenge. But the current migration environment and the computer power now available have made library migrations a routine task yielding enormous time and risk savings and excellent results. Because of these benefits, compaction is extensively used by almost all library vendors.

Fig. 2.14 A Standard Cell Migration

One of the benefits of compaction over linear shrink previously discussed, i.e. adherence to a grid, is critical for contacting the routing around the cells. Supply and ground bars are enlarged as needed and contacts are optimized for gates and well/substrate taps.
All of this is done automatically for the whole process run in batch mode. Nevertheless, if human intervention is needed, it can be done easily as we will discuss later when consider Hard IP creation (not Hard IP reuse) in Chapter 4.