A layout whose functional regularity is also reflected in the layout, such as a memory, has polygons that contribute to a certain electrical function to be performed by a chip placed in an identifiable functional block. It might be said that the layout is modular. For random or irregular layouts, polygons that contribute to a certain function are located all over the chip. This immediately suggests that later, when a layout has to be verified for correctness, it can not be done modularly. This can create problems and is one of the main motivations for trying to maintain a substantial degree of the hierarchy of the source layout during migration. Of course, highly irregular layouts can be migrated. They are migrated flatly. However, a random layout is not the only reason for considering a flat layout migration.

Below are three reasons for considering a flat migration:

  1. As mentioned above, there is no discernible regularity in a layout.
  2. A block is so large that it can not be migrated as a whole. The block needs to be cut into manageable pieces and each smaller piece of the large block is migrated separately. An efficient way to do this is through parallel processing over a network, using several processors. The migration software then puts the many blocks together to reconstitute the original block. However, the layout of the large block is now totally flattened.
  3. While a hierarchical migration has substantial advantages in terms of complexity management, a flat layout is smaller than a hierarchical one. This is because, in retaining its modularity through migration, there are clearly defined geometrical boundaries across which polygons of a certain cell can not move, even if there is empty space that could be filled with polygons from a neighboring cell. So a final run after a full verification of a layout has produced confidence in the “correctness by construction,” might be worth considering.

In Figure 2.17, we illustrate the typical migration of a highly irregular block. As seen in Figure 2.17, the block is cut into manageably sized pieces, each of which is migrated. The cut lines can be chosen intelligently and automatically by the compaction environment. The maximum size of the pieces depends on the state of compaction technology, computer performance and perhaps somewhat on the characteristics of the layout to be migrated. Certain geometrical features in layouts are more compute- intensive than others.

We should keep in mind that for a truly irregular layout, a real layout hierarchy does not exists anyway. The fact that the migration process again yields a completely flat result is not an issue. In addition, flat migration does offer yet another advantage. Flat migration is the most straightforward in terms of setup. What we earlier called the second step in the setup phase, “the trial and error” step, falls away. Because of this, even modular layouts are sometimes migrated flatly. With no setup time to determine the best way to “cut up” a layout into regular arrays, a simple brute force migration is performed “e basla!”

Fig. 2.17 Illustration of a Flat Migration for Random or Regular Layouts


Entire chips can be migrated with substantial benefits. In Figure 2.18, we show how such a migration can be performed. Figure 2.18 graphically depicts how a chip can be migrated while maintaining a relatively “shallow” but rather typical hierarchy. The chip, shown at the top, contains several blocks and the routing to interconnect them.

Each of the blocks may represent any kind of function. The chip in Figure 2.18 shows one possibility. It shows regular blocks like RAM, ROM, PLA, Data path, and an irregular Random Logic block. For the migration, the chip layout will be split into the various major blocks and into the entire routing. The blocks will then be migrated using the most appropriate methodology of the ones previously discussed and maintain the hierarchy to the level discussed in regular structures or be migrated flatly. The identity of the blocks and the hierarchy on the chip is maintained. The routing will be migrated flatly but maintains connectivity with the blocks by being migrated together with the empty shell of the blocks with just the connection points on the boundary (the shell) present. Such empty blocks are generally referred to in the literature as abstract cells. Accordingly, a logical name for this approach is Abstract Cell Compaction or ACC. All of this is quite evident in Figure 2.18.

Fig. 2.18 Hierarchical Migration of a Chip

In terms of IP reuse, ACC offers some significant benefits. One of the critical questions in IP reuse is the chip timing after migration. This is a particularly difficult question if the migrated chip has to be rerouted. As discussed before, timing will be increasingly dominated by interconnects. While we have migrated both the functional blocks and the routing for the chip shown in Figure 2.18, this may not always be possible.

So when migrating from one technology to another, rerouting will strongly affect and change the timing of the circuit to be reused. All the uncertainties corresponding to timing rear their ugly heads. Of course, the expected changes are not as dramatic as starting from scratch. Furthermore, being able to take advantage of additional layers of metal, compared to the “old” layout, may offer enough benefits to justify rerouting. The decision of whether to do a Hard IP migration and conserve the existing routing or to reroute may be affected by time-to-market needs, which could be a forceful argument in favor of Hard IP reuse.

As suggested before, migration will maintain the relative timing of the chip because the relationship between the relative lengths of wires hardly changes at all, although their absolute lengths of wires will change somewhat since everything gets smaller. That is why the important timing, the relative timing relationships in the circuit, should not change much either. This does not guarantee that a timing analysis would be superfluous, but it might be. What it most certainly will mean is a minimal change in the layout to correct a timing problem. For example, such an adjustment could be accomplished with merely a buffer size adjustment. This kind of postlayout (actually postmigration) change can be accomplished easily as we will show when we discuss layout optimization in Chapter 3 and the available tools in Chapter 6.

We have discussed the migration of standard cell libraries, memories and other regular structures, totally irregular structures, a class that covers any block ever encountered and, finally, chips. All of this retargeting was done in Hard IP. What about mixing Soft IP and Hard IP on one chip? And what about analog circuits?

What if one of the blocks in Figure 2.18 were an analog block? For now, the answer is that it can be done and is done routinely by some companies. We will show an example of this kind of a migration in Chapter S, when we examine some of the issues of analog Hard IP migration.

Another challenge: What if the chip migration depicted in Figure 2.18 is extended to take blocks from different sources, blocks that were not on the Same chip before and not even processed by the same foundry? Such a truly S-o-C scenario is possible, but without a doubt challenging. Possible? Probably says the skeptic, most certainly says the optimist. We shall examine some of the arguments in Chapter 5.

Finally, how about mixing and matching Soft IP, Hard IP, analog and making all of this work well in a chip while keeping within the power budget and guaranteeing a highly testable circuit? Well??? Conceptually, even this is possible. Feasible and practical? A marketing department would respond with: Good question! We will address even this issue in Chapter 5.