Let us assume for the moment that the timing behavior of an existing layout in an advanced technology is totally dominated by interconnects. This assumption is not so farfetched since some presently estimate that 70 to 80% of the timing is determined by interconnects, even for 0.18 micron technologies. This means that we are getting close to where most of the power in manipulating for timing optimization in an existing layout is in the wiring and not in the active part of the circuit, even for today's 0.18 micron technologies.
When migrating a chip for Hard IP reuse, the existing floorplan of the blocks on the chip and the routing - the entire layout - is retargeted as such. This retargeting can be done on various levels of sophistication. Retargeting to a new process can be done to satisfy the process rules and the electrical requirements. This is what is done generally when one talks about retargeting. In this chapter, we discuss only this type of retargeting. We discuss optimization issues in conjunction with retargeting later on.
On a more sophisticated level, a chip or a block can also be optimized for performance when it is retargeted to a new process. This approach is discussed in Chapter 3. Such an optimization can be done efficiently only with software driven retargeting that is polygon-based, but not with a linear or a creative linear shrink. Optimization algorithms are also needed to determine what the required optimal layout dimensions. Compaction can only reposition individual polygon edges according to inputs from analysis tools. Of course, migration with optimization is an additional effort. However, it is worthwhile because, as we discuss in Chapter 3, substantial performance improvements can be achieved with simultaneous manipulations of the geometry of transistors and interconnects.
Apart from mitigating the shortcomings of a linear or creative linear shrink, new processes may also bring additional challenges. True retargeting to a new process may in fact require that the layout satisfy additional design rules that did not exist for older processes. Design rules are getting more complicated and new features are constantly being added. Again, this issue can only be addressed with polygon-based compaction.
Figure 2.1 shows a high-level conceptual image of Hard IP retargeting. We can see the inputs needed to start the retargeting process. The target process design rules are required. We also need the original layout data and some performance/timing parameters specified by the user. The original design rules for the various chips to be retargeted are not necessary. We will discuss the details of what is required and what we can expect as outputs in the following sections.
Fig. 2.1 High-level Components of Hard IP Retargeting
In the previous chapters, we outlined some of the reasons Hard IP migration represents a powerful methodology for IP reuse. We will now look at the “conceptual flow” of how migration is done, based on a well established methodology that has been used successfully for many different migration projects. Projects for which this methodology has been used range from standard cell library migrations to chips with well over a million transistors. Although, the discussion reflects experiences gained from a specific migration environment, most of the ideas presented are nevertheless generic and typical of how the principals of Hard IP migration are applied.
In Chapter 1 , we introduced the concept of Hard IP migration without even discussing the input data required, the steps in the migration process, or the output data generated. The goal was just to establish a framework for the discussions in this and the following chapters. Now, we will examine some of the steps for Hard IP migration.
The process of Hard IP engineering is a methodology that offers many variations in how to proceed for a particular project. Because there are so many possible variations in layout manipulation, mastering the details requires working with a particular tool on a regular basis. Pushing today's limits in a technology - and this is what hi-tech chip design is all about - is no less of a challenge than mastering the piano to perform a beautiful classical masterpiece. Clearly, those who referring to such sophistication in design as a push-button operation do not play the piano that well, either. Accordingly, it should not come as a surprise that dealing with every layout feature that could ever be encountered in Hard IP migration requires skill and experience, the same as for any design methodology dealing with the complexity of multimillion transistor chips.
In this chapter, and in fact in this book, there is a constant trade-off between describing the details of how to exactly adjust a certain layout feature and how Hard IP engineering is done conceptually. The goal is to give a good idea of the basics of Hard IP migration. For the very detailed knowledge needed for the actual day-to-day problems faced by a those doing Hard IP migration, there arc manuals and, it is to be hoped, good engineering support. The manual and the engineering support come into the picture when a user of a migration methodology gets “stuck.” In the following discussions, we remain on the conceptual level to avoid getting “stuck,” while still providing a good understanding of the process.
We show details, such as the exact format or syntax of the data required for a particular job, only when they contribute to understanding of “the big picture.”