Some of the layout geometries determine whether a circuit will function and whether it will function reliably over a long period of time and under adverse environmental conditions. Many of these layout parameters are literally prescribed by the processing technology used to fabricate the chip and because of this very close connection to processing, they are specified in the processing file. As such they tell the layout or migration tools what they are allowed to do, and they need to be part of the specifications for any chip, irrespective of its electrical function. They are parameters that generally need to be respected to prevent catastrophic chip failures, not just inadequate performance.

Some of these issues are:

1. Latch-up has been a curse for an otherwise almost perfect technology, the CMOS technology. Years of experience have largely eliminated this problem. For any particular process, foundries give strict layout guidelines. If followed, latch-up will not present any problems. These layout rules are simply put into the process file and the layout tool or the migration tool will take them into account. It generally boils down to placing a lot of contacts in strategic places, which is particularly easy to do with retargeting. We will later show an example of how this can be accomplished elegantly and time-efficiently in the migration process.
2. Electromigration is another very destructive phenomenon in chips. The maximum allowable current density for minimizing electromigration is a key factor that determines the minimum metal width. It is the responsibility of more than one person to obtain the correct values. In fact, the specification of a current density through metal interconnects to stay below a certain value to prevent electromigration involves many disciplines. Just how much current can flow through a certain metal width depends on the thickness, the profile of the etched metal line, the temperature of the metal when the circuit is in operation, the chemical composition of the metal lines, etc. Also, the tendency for hotspots to occur on chips, and not just the overall temperature of the metal during operation of a chip, is particularly crucial to the long-term reliability of a circuit.

Data on electromigration are generally based on years of research and experimentation. That is why the way to create metalization with the highest possible current density is part of the carefully guarded technical know-how of chip fabrication companies. This is subject to intensive research because it is so crucial to chip performance and maximum allowable current densities keep increasing. Maximum current densities, a benefit from the latest technological advances, depend on the latest discoveries of metalization “additives.” This is why the close cooperation of many disciplines, reflecting a lot of experience, is necessary to get the most appropriate values. Needless to say, there may be substantia! differences between the current capabilities of various foundries.

Since current carrying capability of chip metalization is so critical to layout density and reliability, it is well worth paying attention to potentially sporadic advances in this area and taking advantage of them. This factor alone may justify changing foundries. It is a strong argument for using retargeting with the compaction methodology, since this allows this type of switch after a few computer runs to implement the new process design rules and optimize timing as needed.

“Migration engineering” is such a powerful methodology because there is a very direct and close relationship between performance of a chip and its layout geometries. This is particularly true for MOS technologies. It is less true for chips with bipolar junction devices or with a mixture of various types of devices, where vertical geometries such as junction depths are just as important or even more so. This observation immediately suggests that chips with a mixture of devices must be treated differently. We will here focus on MOS technologies.

Of course, parameters related to vertical geometries such as oxide thickness, k-factors of the oxide, interconnect metal thickness, junction depths, etc., are also critical to MOS technologies. I-Iowever, they are primarily process-related parameters and, in terms of chip design or migration, they are simply design parameters that have to be accepted.

We will concentrate on horizontal (layout) geometries, focusing on postmigration first time success and performance optimization.

With a clear focus on layout geometries, horizontal geometries have various degrees of influence on the migrated layout. They can be ranked in significance from destructive, if not satisfied, to values required to achieve optimized performance of a migrated chip. We will now examine these layout parameters.

How well can one guarantee a migrated chip that is both fully functional and correct in terms of timing?

Of course, guarantee really means that it is based on the best engineering analysis and judgment. Even a full simulation/verification cycle may not be able to guarantee first time success for a complex VLSI chip. In the DSM area, first time success is even more difficult to guarantee. We know the physics, but this knowledge is not always easy to apply. Even in pre-DSM days, the promise of “correct by construction” was often more a marketing slogan than reality. However, since DSM “surprises” are fundamentally layout-geometry-based, intelligent layout and postlayout engineering can alleviate many of the problems. The tighter the link to the back-end in the design cycle, the more successfully DSM surprises can be avoided. Clearly, Hard IP engineering is not just a powerful link to the back-end.

Hard IP is the back-end!

Some layout geometries are enforced to influence the electrical behavior of a chip, others to affect the timing behavior. Electrical requirements, such as not to exceed a certain resistance or a certain voltage drop in a metal interconnect, are satisfied by specification of certain parameters. The preservation of timing relationships through the migration process is intimately related to how migration or postlayout optimization is done. We will now discuss how to affect both of them.

As previously stated, a key reason for IP reuse is to benefit from former engineering investments, to minimize additional engineering investments while possibly enhancing performance, to increase the number of functionalities with S-o-C and, at the same time, minimize the time-to-market. We have already explained that Hard IP migration preserves the functionality of a chip. A migrated chip's satisfying all the layout rules is enforced by the migration software, if all the processing and migration files are set up correctly. This needs to be checked. The good news is that checking a very small piece of a migrated layout is sufficient to check the correctness of the process file setup. The remaining issue is the migrated chip timing . Why should the timing of the migrated chip still be OK?

Timing in digital circuits and timing in analog circuits can not be treated the same. We will discuss the challenge of IP reuse for analog circuits later, but timing is definitely not the only difficulty that needs to be addressed for analog circuits. For now, we will address only Hard IP migration of digital circuits.

Having to deal with the signal processing of only digital signals has many advantages. Many of these advantages are well known and need not be enumerated here. There are, however, some interesting issues that need to be pointed out that are critical for explaining why digital chips keep on working, even if parasitic capacitances (especially interconnect parasitics) have not been accurately determined. This is particularly interesting for DSM technologies where interconnects are starting to determine the limits of the speed of a chip.

For now, the following broad statement gives an idea of one key timing issue:

The most critical aspect of chip timing affected by interconnect delays is relative timing between the various signal paths. While the chip speeds up, the timing relationship between the signals should be maintained.

Accordingly, the relative timing between signals is much more critical than the absolute delay of any one of them for digital circuits to work with respect to timing. On the other hand, the actual delays are more critical for the overall speed of the circuit. In other words, a circuit fails when the time relationship between certain signals is off. When a circuit's absolute delays are off, it runs either faster or slower than expected but will still work.

The more interconnects 011 a chip dominate the timing, the more a balance and a relationships between the lengths and the parasitics of interconnects should be maintained. For a linear shrink, this is very much the case. For compaction, this is sufficiently maintained for the relative timing to also remain unchanged. This is in big contrast to what would happen if the chip were rerouted as it is taken from one process to another. Therefore, keeping the routing of the “old” chip not only saves time and money but significantly lowers the risk that the chip in the new process will have a completely different absolute and relative timing.

Signal delays must be calculated accurately to predict the time performance of a digital circuit. Thus, if interconnects dominate timing, the delay characteristics of the interconnects must be accurately calculated. A discussion of how to determine delay and other characteristics is presented in Chapter 3. For now, we merely wish to state that the delay characteristics turn out quite accurately, with approximations generally made to obtain calculated results with manageable efforts. We will see why in Chapter 3. We will also see that some other critical parameters suffer in this approximation process and are way off.