As a first order approach, as both W and L of transistors are reduced in accordance with the new process rules, the W/L ratio of the transistor gates should be kept at the premigration values, instead of both W and the L being changed to the minimally allowed dimensions. This should maintain liming relationships between the transistors consistent with the original, premigration circuit.

For a linear shrink, W/L remains unchanged automatically. It has to be specified for compaction. The advantage of this, however, is that the W/L ratio can be anything we want it to be. This flexibility will be useful for optimization.

Furthermore, while the W/L ratios of the transistor gates are the most obvious layout dimensions not to be minimized as allowed by processing, other layout dimensions may also have to be different from the minimum values allowed by processing. Some, as mentioned before, because of reliability, others because of the electrical criteria of the chip or for reasons of manufacturability. Some of these layout dimensions are generic to the process and the same for all the chips to be fabricated in a certain process. Others are related to the performance of a particular circuit. Even EDA layout software is often automatically laid out to the minimum allowed dimensions specified by the process file.

Finally, let us assume a chip is migrated from an old process (e.g. 0.8 microns) to an aggressive technology (e.g. 0.18 microns). The timing of the migrated chip will change due to both the change in the speed of the active devices as well as the interconnects. Even in this case, some of the arguments for maintaining the relative liming may still apply to a certain degree, especially for the interconnects, since they all get reduced together. Of course, the timing of the chip for such a large step in technology makes a rather radical change from being active-device-dominated to interconnect-dominated. This is a good example of a situation where large changes in transistor W/L. may be needed to “gel the timing back.” However, adjustments in transistor W/L ratios may not suffice to fix the timing discrepancies resulting from such a large jump in technologies. However, more than just W/L can be adjusted in a layout to bring the timing in line, as we suggest in the next section and discuss in more detail in Chapter 3.


The fact that VLSI circuit transistors traditionally controlled largely the timing is still evidenced by the fact that there are currently no commercial tools available that go beyond focusing on transistor modifications to adjust the timing. While compaction can modify any layout geometry to any desired value within the available space, the decision on how much to change must come from other tools. Presently, however, only university-level algorithms are able to analyze more than transistors. This is unfortunate, as we will see in Chapter 3. We will show that the layout timing can be changed dramatically if we modify both transistors' W/L ratios as well as the load they are driving, the interconnects. These simultaneous modifications will be the basis for some serious layout-based performance optimization.


We will now examine the various steps of a migration. We consider the input data required, how to influence the path the migration process follows and, finally, how we can use the data emerging from the migration process to reiterate the migration steps and even to modify processing.

We are starting the Hard IP migration process with data describing physical layout as “source” layout. This source layout represents a fully functional block or chip in some MOS technology. The layout data contains everything needed to produce a chip. Every polygon-edge position in this layout is precisely defined.

The source of this database may be from a VLSI circuit, designed by one or a mixture of design methodologies. Circuits based on any design methodology can be migrated, ranging from handcrafted to field programmable, although it may make sense to migrate a field-programmable device only in conjunction with other circuitry on a chip. It all depends on how much value there is in reuse, compared to redesign of a particular circuit function. In fact, what may represent a design for Hard IP that is worthwhile to migrate will be easier to decide later in this book, after we have a feel for the effort required for Hard IP migration versus the benefits.

Depending on the methodology used for a design, the layout may be more or less optimized. A fully custom design may be optimized based on the best criteria at the time of the design or just for the particular process for which it was designed. Other designs may have been done based on older libraries. Whatever the reasons, there is usually room for improvement. Hard IP engineering allows such improvements at postlayout, no matter what design methodology was used. Then, the knowledge gained from the layout-based performance improvements can often even be used to fine-tune a process, as we will discuss in more detail in Sections 2.4.3 and 2.4.4.

We all know that the demands for performance made on today's VLSI-based designs and chips are very high. Let us look at what type of improvements we can achieve with the compaction methodologies discussed here. First, we examine the input data required to migrate a design, including user-specified parameters to steer the compaction process towards the desired results. In contrast to layout optimization which is discussed in Chapter 3, the main goal here is to retarget an existing design and obtain a reliable, functional and timing correct migrated design. We will now explore the various steps and approaches we can take towards achieving the desired results.


We suggested earlier that there are three phases in a migration without an optimization cycle.

A first phase is setting up a system for migrating a layout and setting up the process files. This phase may take some labor but is not difficult. We just need to make sure there are no errors in the process files.

A second phase concerns exactly how to go about migrating a design. This is the phase for setting up the proper conditions for a compaction run. Migrating a simple little block, a library, a memory, a complex chip or even a mixture of chips for a S-o-C solution are all possibilities. There are many variations, depending on the nature of the design to be migrated. Trade-offs are generally between the time and effort required to set up the process versus the quality of the results, the ease with which the resulting layout can be verified. Should we migrate a chip or block hierarchically or flatly? Should regularity in the layout be taken advantage of during migration? Should routing be migrated separately, as part of some blocks? Or would rerouting even make sense in some cases?

Time spent properly setting up for migration is comparable to good planning for any project. If done well, there is usually a good return on the investment. And, as with any engineering tools, experienced users will get better results.

A third and final phase is the compaction run lime. This should be push-button and very predictable. Once the retargeting environment has been properly set up and good results have been achieved, a rerun of the compactor with modified process rules is straightforward and just a matter of computer run time. This is the reason why making last minute adjustments is easy and fast and can produce great benefits in performance and, potentially, optimization of the process. Considering the rate at which processing technologies are changing, last minute retargeting always seems beneficial.