In Figure 2.4, we show the migration environment that serves as a basis for discussions in this chapter. Figure 2.4 illustrates the basic process and the data components to be specified for Hard IP migration. The polygon-compaction engine as illustrated in Figure 2.4 is at the heart of the migration process. Most of the discussions will be based on one-dimensional compaction. One-dimensional compaction is compaction along the directions of the orthogonal coordinate system. Polygons move along the x-coordinates and along the y-coordinates, one at a time. To show the benefits derived from compaction and to understand how to optimally affect the results, we have to examine the input data required, the process of compaction and, finally, the outputs resulting from the compaction process.

Fig. 2.4 The Major Components of a Migration Environment

Data to be specified for compaction

Figure 2.4 makes it clear that we need to specify

Figure 2.4 is a simplistic, high-level conceptual view of both inputs and outputs in a migration environment. This is the minimum data that has to be specified to make migration possible, and we will discuss this now. Later, we will examine additional possibilities to determine how layout manipulations can be used to optimize circuit performance, utilizing the techniques discussed here, or yield a new process, with or without migrating them.


The compaction engine works on the layout of the blocks or chip to be migrated. If the compaction is one-dimensional, it will be performed on the source data in any desired order. The x-axis can be compacted first and then the y-axis or vice versa as chosen by the user. The quality of the results may differ, depending on the order. Since we have been discussing process-parameter-based design rules, we are exploring how feedback from the compactor can show the influence of certain design rules on the retargeted layout.

In Figure 2.5, we show a migrated layout along with feedback from the migration engine. In the layout, we see straight, fine, yellow lines that highlight polygon edges along these lines. In the illustration on the left, these lines are vertical while the separations between them along the x-direction indicate a critical path in the x-direction. In the illustration on the right, the lines are horizontal while the separation between them indicate a critical path in the y-direction. In both directions, these paths represent a layout-related critical path.

Critical path means that all polygon edges along this path are at the minimum distance from each other as allowed by the process-based or any other design rules. This is the highest density that can be achieved without violating the design rules along the critical path. This critical path can be an indication of the quality of a layout. For instance, in a memory array, the polygons delimiting the memory cells should be as closely placed to each other as the process allows, because they determine the packing density of the memory array. Any dimensions larger than the minimum possible for the cells are multiplied many times in the array, yielding a memory array that is larger than necessary.

Fig. 2.5 The Concept of “Critical Path” in Layout Migration

In Figure 2.6, we show how utilizing the knowledge of the critical path in a layout as feedback from a compaction run can be used to improve the layout. We see that in the chain of cells on the left side of the illustration. In the cell farthest to the right, the L-shaped metal line in the upper right corner gets as close to the metal line next to it as is allowed by process rules. The cell farthest to the right is therefore the highest cell and determines the height of all the other cells, because pitch matching requires this. With a minor manual intervention in a layout, we can change an entire standard cell row. Just moving the L-shaped metal line “knee” shown in Figure 2.6 along the critical path in the metal layer to the right just a small amount will give the compactor the freedom to reduce the height of the cell farthest to the right and, accordingly, all cells shown on the right of Figure 2.6. A small increase in the length of the chain of cells may result in significant savings in the total area of the standard cell chain.

Fig. 2.6 CriLical Path Information for a Chain of Abutted Cells

In Figure 2.5, we showed a path along which all dimensions are at a minimum. It is also interesting to know which of the minimum geometries of the process parameters cause the highest number of polygon edges in a layout to be placed at the minimally allowed separations. This may be a “point of negotiation” with a processing engineer. We show this type of information in the following section on statistical feedback.