The statistical data displayed in Figure 2.7 lists the number of times a certain layout geometry reaches the minimum as prescribed by a particular process rule.

This data is based on a specific layout and varies from layout to layout. For the data in Figure 2.7, the layout is a RAM cell.

The table contains the following information:

  1. The first column is the name of a design rule defined in the process file.
  2. The second column is the value of this rule.
  3. The third column is the number of layout geometries using this design rule.
  4. The fourth column is the percentage of the cell dimensions using this rule.
  5. The fifth column is the part of the cell dimension following this design rule.

The most obviously useful column is the fourth, showing the percentage. In the example given here, the dominance of one rule limiting a further reduction of the layout dimensions of a cell is not very great. Still, if that one rule could be relaxed a bit from the processing point of view, the RAM cell could become smaller. For a RAM or ROM cell that is repeated millions of times, even a minor change can make a big difference.

Fig. 2.7 Feedback on Where Maximum Density has Been Reached

Statistical feedback suggests the following observations:

  1. The one layout dimension, that “pushes” against the process design rule (here W701), may be tweaked in the process. For a process specifically designed for memories, this may be worthwhile.
  2. As a consumer looking for foundries, it might be worthwhile looking at various competing foundries. Needless to say, that gives a consumer some valuable negotiating power.
  3. The statistical data might suggest to the designer of the migrated circuit how to make some minor changes in design to further reduce chip sizes. However, a certain dimension that occurs in a layout so many times may be difficult to change.