In the last few years, Hard IP reuse has been focusing on retargeting. Even now, when the engineering community talks about Hard IP, retargeting always seems to be the primary focus. The main reason for this may be the gap that has developed between manufacturing capability and design productivity of DSM VLSI chips, calling for ways to bridge that gap. Hard IP reuse is viewed as an approach that at least narrows the gap.

Compaction technology is at the heart of a sophisticated Hard IP reuse or retargeting. Since compaction allows a manipulation of physical layout geometries at the polygon level and since DSM VLSI chip performance and manufacturing yield are very sensitive to layout geometries, compaction should allow us to optimize both performance and yield in addition to providing just a re-layout of an existing Hard IP according to new process parameters.

In this chapter, we discuss how we can improve performance through layout manipulations. In Chapter 4, we discuss how we can improve yield through layout manipulations. We already suggested some of the capabilities for improving yield in Chapter 2. In this chapter we look at this issue in considerably more detail, discussing Design for Manufacturing (DfM), in which compaction plays a key role.

Of course, every additional step in a design or reuse flow adds more time. In a world in which the time-to-market aspect is potentially the most critical aspect to success of a VLSI chip, this is a legitimate concern. On the other hand, if a migrated chip or any chip that might have been designed from scratch or with Soft IP reuse does not meet performance specifications, using compaction for postlayout optimization could provide a relatively painless and quick fix instead of more drastic, riskier or time-consuming measures. Similar arguments are applicable if the manufacturing yield of a chip is not high enough. Finally, it is to be expected that with advances in processing technology towards smaller and smaller minimum dimensions, challenges, especially for timing closure, will only become greater. Large VLSI chips that are correct the first time may be even harder to achieve. Compaction as a postlayout step can be of great help in eliminating these kinds of problems.

Only the question remains:
How much can actually be done with postlayout manipulations using compaction in terms of performance? This chapter examines this issue.


We have discussed how VLSI chips are now the core building blocks for information management in hi-tech electronics. We have stressed the need for high performance, emphasizing key parameters such as speed, power dissipation and miniaturization, which is also packing density. We will now explore how to manipulate a VLSI layout to affect these performance parameters. For this, we need to examine analyses performed over the years to evaluate the influence of physical layout parameters on key VLSI chip performance parameters.

As we examine some of these analyses, we will constantly confront the dilemma of having to make approximations. Today's VLSI chips are simply so complex that most analysis will be too time-consuming or impossible without approximations. Approximating, while sacrificing as little accuracy as possible, generally requires setting priorities that favor certain parameters.
We need to try to achieve as much accuracy as possible and simplicity, we hope, for parameters that are the most critical for a particular application. Accordingly, we need to establish the most critical performance parameters for various applications. Later in this chapter, we will see how focusing on determining certain performance parameters requires approximations that, while perfectly acceptable for the desired results, would lead to invalid or inaccurate results if blindly used to determine different performance parameters. It is therefore critical for layout optimization to use data compatible with the goal of the optimization.

Different areas of application require an emphasis on different performance measures. For computers, a dominant measure of performance is the speed with which operations can be performed. For wireless telephony, smallness and power consumption are for obvious reasons dominant factors, although speed, generally measured in bandwidth requirements, is also terribly important. Of course, power consumption is in general extremely critical for anything portable, due to battery life. However, even if battery life is not a concern, limiting power dissipation is gradually becoming a simple question of “survival” for a chip.

There are many more areas of application with other key factors, but many of them arc related in some ways to the ones we have listed as major concerns.

The extremely rapid progress in VLSI chip performance, due to enormous advancements in processing technology, does not come without a substantial price tag for modern and improved processing lines. Yet, in spite of the astronomical cost of newer processing lines, there presently does not seem to be any slowdown in processing capability advances. In fact, when comparing performance improvements due to advances in clever design techniques versus processing technology, processing technology wins hands down. The least we can do, and have to do, to reward such progress and take these enormous investments into account is to try everything possible to get the maximum benefits out of these expensive processing lines.


Actually, the statements above already emphasize the importance of physical layout geometries for performance, without any further discussions. Why would anybody spend so much money if there were no substantial benefits?

The manufacture of smaller and smaller minimal critical physical dimensions and larger chips arc the most directly visible measures considered responsible for increased performances. However, the ultimate performance of a VLSI chip is actually a very important function of not only the minimum critical dimensions but also of many other dimensions of the physical layout. In addition, optimizing the layout geometries of a chip takes only some engineering effort and time, the expense of the software and some computer runs.

We already know that the lengths of interconnects play a dominant role in performance and that the placement of intercommunicating blocks is very critical. This is rather obvious. However, do we also know how the length of interconnects and the remaining dimensional parameters of interconnects affect DSM VLSI chip performance?

A considerable amount of research, mostly at the university level, has been done to determine how to maximize the speed and minimize the power consumption of DSM VLSI chips with detailed physical layout manipulations [3], The focus of the research was on how to dimension interconnects, the drivers, or even interconnects and drivers as pairs simultaneously. Other parameters such as signal integrity, reliability and yield will also be affected. We discuss some of the results in detail later in the chapter.

The physical layout of a DSM VLSI chip has to be developed with a lot of care during floorplanning and the placement and route design phase. This is by now universally recognized for hi-tech VLSI chip design. The ability to intelligently address the physical layout design very early in the design cycle is a hot issue for front-end, high-level methodologies like synthesis and progress is being made. However, as the minimum layout dimensions become smaller, the timing uncertainties grow until a layout is complete.

Fortunately, there is a lot of postlayout optimization that can be done at the back-end using compaction.

This is of interest even for VLSI chips that have just been designed using the latest, most advanced, functional level synthesis techniques that have taken account of the back-end, the physical layout.

Needless to say, it is also of considerable interest for IP reuse, especially Soft IP. These “established” chips may not have benefited from the latest front-end tools that take account of physical layout, but they still have too much to offer to just be thrown away. In addition, it is clear that chips migrated to faster, more advanced processes as discussed in Chapter 2 could use a postlayout tune-up. This type of layout manipulation can maximize the speed of both of these candidates or minimize their power consumption, or both.

Just how much postlayout optimization contributes to performance improvements and how much is needed to make it worthwhile depends on many factors?

If we were to assume only, let's say, a 10% improvement, this 10% could persuade a customer to choose one product over another. With the big bucks in electronics being increasingly spent on consumer electronics, this is clearly important. If the improvement was only 5% but would save a complex microprocessor chip from failure, it would be worthwhile. As we will see later in this chapter, most of the time there is much more to be gained in performance than just a 5 or 10% improvement.

We will now discuss how layout manipulations will help improve performance and manufacturing yield of a fully laid-out chip by optimally dimensioning interconnects, drivers or by optimizing the interconnects with the transistor stages driving them as a pair.