Much important research has been conducted over the years to examine the electrical and timing characteristics of interconnect structures. Actually, some of the most useful work analyzing interconnect parasitic capacitances was done as far back as 1973 [4]. Of course, in those days the performance of VLSI chips was not affected by interconnects on the chip. However, for various other structures such as PCBs, MCMs and especially strip lines for memory arrays, problems existed that are very similar to what happens now on DSM VLSI chips. However, while the work to be discussed here addresses physical layout issues and covers such a long time period (compared to the newness of VLSI technology), the points of emphasis and interest kept shifting over the years, as we will see. It started with layout-related timing analysis and only very recently has there been a significant interest in true physical layout optimization, which still seems to be limited to the academic community[3 ].

The following discussions are based on some of the work done over the last twenty-five years that is related in one way or another to signal propagation in VLSI chips. However, despite the early 1973 work, the literature search was very focused. Only the most pertinent, most recent work that directly addresses the interconnect issues in DSM VLSI chips has been reviewed. Furthermore, for now the discussions will largely concern timing and power consumption issues. Other important issues such as cross-talk and signal integrity will also be addressed.

In the 70s, as suggested above, the focus was on determining the parasitic capacitance values of interconnects different than what we find on DSM VLSI chips today. However, the work dating back to 1973 does an excellent job of yielding many results that are difficult to find in the current literature. We will make considerable use of this information. Although this was long before DSM effects became critical for VLSI chips, the interconnect capacitance parasitics the active parts of the circuit (the transistors) have to drive are conceptually very similar. This is especially true of current popular MOS technology, for which the dominant effect of resistance-capacitance time constants are significant because of the high impedance levels. Interconnects could still be modeled with a simple, discrete RC load. Also, ICs were still small enough to be simulated with SPICE or SPICE-like simulators.

In the late 70s and early 80s, all VLSI chip components could be modeled as discrete components, all except for the base resistance in bipolar transistors, which was already a nonlinear, distributed RC load. Accordingly, the challenge of dealing with distributed loads in VLSI chip analysis has been around for quite some time. Simple discrete RC models where used for interconnects, except for very fast circuits and critical interconnects. By 1983 [5], as chips became too large for SPICE-like simulators, switch-level models and Timing Analyzers (TAs) became popular.

By the mid 80s, MOS technologies started to dominate bipolar technologies. However, by this time, interconnects started to behave like distributed RC loads. In fact, for high- speed applications, interconnects started to behave like a lossy RC transmission lines. Determining signal propagation along RC transmission lines presented a serious mathematical challenge. There exists no closed form solution in the time domain [6], Timing analysis had to settle for determining bounds as opposed to exact timing information and exact pulse shapes. Contributions to lime delays were more or less equally shared between the active and the passive parts of the LSI circuits.

However, the ability to model one lossy RC line between two drivers was not enough. The signal distribution in a VLSI circuit was done by complicated RC tree structures. Models were needed for RC tree structures and became available in combination with switch-level-based TAs in the mid 80s [7].

By the latter part of the 80s, interconnect delays became critical and dominant enough to require a rather detailed timing analysis for critical RC trees, such as clocking trees. However, as processing technology kept marching relentlessly forward, it became clear that interconnects would eventually dominate the timing behavior of VLSI chips. Some simple, straightforward measures were needed to gauge the effects of shrinking layout geometries on VLSI chip behavior. Scaling factors became popular for showing trends in chip performance, as a result of smaller critical layout dimensions. The scaling factors showed how changes in physical dimensions, such as the interconnect thickness, width, separation, length, the oxide thickness, etc., would affect the behavior of the VLSI chip [8].

The end of the 80s and early 90s were marked by attempts to approximate parasitic capacitance values and the time delays caused by them with relatively simple analytical expressions [9], These analytical expressions have to be applied with full knowledge of the assumptions made in their approximations. In studying the effects of interconnects on time delay, it became clear that short interconnects between drivers would not substantially increase signal delays, but that long ones would. Studies were conducted on the statistical frequency of the occurrence of long versus short interconnects. The conclusion was that short interconnects are much more frequent than long ones [8], Buffer stages would be inserted for the long ones, to keep them from getting too long [8], At least, this is the present conventional wisdom.


A good floorplan and a good place and route based on timing-driven layout tools is about as much as one can do to approach the desired performance of a DSM VLSI chip. However, most timing information available before a layout is completely statistical and based on previous similar designs, of which there are generally very few. Although constant progress is being made in forward annotating tools, the processing technology also keeps moving at a rapid rate.
The challenges of obtaining first-time timing-closure are growing and so is the need for some type of postlayout optimization. Of course, the closer the chip to correct timing based on the synthesis, floorplan, and place and route, the greater the chance for success. And postlayout optimization can not work if the timing is completely off.

In the 90s and beyond, ignoring intuition, a substantial amount of research has fortunately been conducted on true layout optimization [3], As we shall see, some of the results are amazing and impressive.

As chip speeds keep increasing, as packing density increases and chips get larger, dealing with the heat generated in these chips is one of the most serious challenges. In fact, at least one startup claims that power dissipation is the single most limiting parameter seriously hampering - if not blocking - some DSM VLSI chips from becoming a reality [10].

So we need to explore every possibility for minimizing the power generated on the chip without giving up speed. Clearly, inserting buffer stages into the interconnects increases power consumption and takes up real estate, increasing chip size and increasing its cost and without adding functionality. It is taking us in an undesirable direction.

Of course, we have to pose the legitimate questions: How can we achieve the necessary speed without these buffer stages? Could we find other ways to maximize speed without an increase in power consumption?

The most obvious question concerns the optimal sizing of every transistor in a VLSI chip. Every transistor that has more driving power than absolutely necessary burns unnecessary power and is also wasting real estate. Transistor sizes are generally adjusted by searching for a critical path, the slowest path on a chip, in order to then adjust its driving capacity. The search is not primarily for devices that are potentially too large. The critical path determines the transistors that are too small. To minimize power consumption without slowing down a chip, the goal has to be to optimize the size of every transistor in a chip.

A less obvious question concerns the dimensioning of interconnects. After all, we know that they greatly affect the speed of a VLSI chip. But how and by how much do interconnects affect power dissipation?

The answer lies in the load the interconnects represent, which the transistors have to drive.

An optimal dimensioning of the interconnects in conjunction with the transistors that drive them may allow smaller transistors and less power consumption without sacrificing speed performance, or even improve both parameters.

Recent research supports such statements [3] and has shown some remarkable results. As opposed to changing a given design, the emphasis is on optimizing existing designs with a sharp focus on physical layout optimization. We will discuss some of the results later in this chapter and see how the methodologies in Hard IP migration can implement the layout modification suggested by such findings to optimize DSM VLSI chip performance.

This brief overview should motivate us to explore just how much layout-related parameters can affect final DSM VLSI chip performance. We will examine both the front-end and back-end leverage to assess their level of significance.