So far, we have discussed Hard IP reuse and Hard IP optimization. We will now examine Hard IP creation, how to create it more efficiently, more conveniently and how to create denser layouts than otherwise possible. Creating Hard IP produces an IC layout of a new standard cell, memory cell, generator, instance or custom block.

When designing the layout of such building blocks that are used over and over again, it is worth the time and investment to create the densest possible layout. Every micron counts, especially for memory cells that are placed in arrays in great numbers of repetitive cells. Just as critical are performance and power consumption parameters, but those will be discussed later.

The bottom line, the key to company success is of course to create denser, higher performance layouts than the competition and create them faster. Also, as processing parameters keep changing, and they are currently changing rapidly, layouts have to be rapidly retargeted. A design approach well balanced in terms of human input and computer aid, such as a powerful compaction engine seamlessly integrated into a state-of-the-art layout editor, is worth considering.

We have so far discussed the use of compaction when a layout already exists and needs to be either retargeted to a new process or has to be optimized for the best possible chip performance. We will now introduce an approach using compaction that offers the benefits of both IC layout design rule correctness and optimization of layout density, built directly into the IC layout design flow.

First, we compare a traditional IC layout flow with one where compaction is part of the design flow. On the left side, Figure 4.1 shows Hard IP creation based on a traditional approach, and on the right side using compaction. Both flows start with what is generally referred to as topological design. During this phase, the layout topology is drawn on a trial and error basis, using approximate locations to determine how the polygons and larger pieces can be fit together to create a nicely laid out cell. In this step, the layout designer should not have to worry about design rules imposed by processing, rules dictated by the desired electrical behavior of this building block, including possibly yield criteria, maximum power, current consumption, etc.. These are a lot of complicated rules to bear in mind.

The left side of Figure 4.1 shows a traditional IC layout design flow, where a designer puts a lot of effort into fixing DRC errors. On the right side is a compaction-based IC layout design flow, where the designer is free from worries about process-imposed layout rules.
As we can see from the compaction-assisted IC layout on the right of Figure 4.1, the focus so far is only on design rule correctness (DRC), which can also address yield enhancements, as previously discussed for DfM, and maximize layout density.

Fig. 4.1 Traditional and Compaction-Based IC Layout Design

This range of solutions is commercially available today in products used in the field. Although these solutions address only a subset of what is possible with compaction, they already represent great steps forward for many reasons, which will be enumerated in the next section.
Looking a bit into the future, we should keep in mind the postlayout optimizations for performance and power, as discussed in Chapter 3. In principle, these additional features are not difficult to implement but tools including them are not presently commercially available.