The main goal of compaction-assisted IC layout is, of course, to help the layout designer create the densest IC layout he can, as fast as possible and with minimum risks.
With the traditional layout flow, the multiplicity of rules to be
respected clouds a layout designer's vision, reducing his layout
creativity because he can not focus fully on the topological design
process. After all, the layout will have to pass DRC for the cell
layout to be acceptable.
As we know from experience, the best work is always done when one can focus on the most important aspects of a task. The key is to separate the tasks into what requires what humans can offer, such as creativity, and tasks that the computer can do much faster and more reliably with the aid of software, keeping track of data. That is what is shown in the flow on the right side of Figure 4.1.
The compaction engine with its process files keeps track of all the complex process layout rules, while the layout designer can freely experiment with various trials without design rule errors, focusing on the most clever topological design that fits the rest of the circuitry. Using the compaction-based flow, the designer can concentrate fully on the layout activity. The compaction engine acts as an online checker, giving instant feedback to allow corrections to be made interactively. The layout designer can leave it to a compaction step immediately after the “experimental,” loosely drawn placement of the layout features to enforce all the rules and user inputs.
As we can see on the right side of Figure 4.1, there exists adensity optimization step for the compaction-assisted flow. As already discussed in Chapter 2, compaction yields immediately feedback on critical paths, the path that shows where minor modifications in a physical layout can lead to significant density improvements. We have seen in Figure 2.6 in Chapter 2 how a minor change in layout can significantly change the layout density. Figures 2.7 and 2.9 showed how jogging (doglegs) can help layout density along critical paths. Jogging is automatically inserted into the layout by the compaction engine, if the user desires. This does not require manual effort of the user.
Finally, since compaction is one dimensional, rapid what if x first then y or y first then x compactions can show the layout designer which compaction sequence may lead to a better layout. Accordingly, the designer can modify his layout on the fly to achieve a design-rule-correct and a much higher density layout than what was possible without this feedback in the traditional layout approach. Furthermore, and as indicated in Figure 4.1, the traditional approach results in a recursive loop between the initial layout and the DRC just to get the layout so that it might pass DRC. Recursive loops cost valuable time. The compaction-based IC layout flow shown in Figure 4.1 demonstrates the basic steps required. For a complete design environment using compaction, the flow in Figure 4.1 needs to be integrated seamlessly into current DSM VLSI chip design environments, as shown in Figure 4.2.
Fig. 4.2 Compaction-Based, Commercial Layout Design Environment
In Chapter 6, when discussing actual commercial solutions, we will show the same flow integrated with commercially available software.
Although, the solution shown in Figure 4.2 is a workable flow for compaction-assisted IC layout design, it shows only part of what in principle is possible. It really shows only the IC layout rules perspective. In Figure 4.2, there is no device and no interconnect sizing analysis software for power and performance optimization. Furthermore, current generically employed design flows of complex DSM VLSI chips do not take advantage of compaction, but this should change. Compaction can implement many desired changes to achieve the performance needed at a time when all other means of change have been exhausted. Even with the limited compaction-assisted flow shown in Figure 4.2, the following present and future compaction-induced consequences are worth mentioning.
At present, the following technical and organizational aspects of IC layout design (also many aspects of DSM VLSI chip design) can be made easier, faster and more reliable using a compaction-assisted IC layout design flow:
Future, potential benefits that do not presently seem to be
implemented (except for perhaps in some of the more progressive
companies) are sophisticated performance and power optimization
features that address simultaneous transistor and interconnect
dimensions as discussed in Chapter 3. These features are technically
already feasible. A flow should be created that analyzes cells, larger
blocks, custom designs for optimally dimensioned transistor and
interconnect dimensions. This type of information should then be
interactively fed back to the IC layout designer. This could be done as
soon as the industry has adopted some of the optimization algorithms
discussed in Chapter 3.
Why not create an optimal IC layout, not just one with maximum density, good yield and without any layout design rule violations? Why not optimize speed and power performance during the IC layout?
In summary, all the typical features contained in a state-of-the-art compaction engine as discussed in Chapter 2 are available to an IC layout designer. Features such as the abutment of cells, gridding for ports to guarantee connections to routed interconnects and automatic jog insertions in critical paths are useful for getting a top quality layout in a minimum time and with minimum effort. Keep-out regions are respected, as often required by metals, ports, analog layouts, etc. The design database indicated in Figure 4.2 contains not only physical layout data but also pin and connectivity information, and this data is maintained through the compaction process.
Compaction-assisted IC layout can also create additional space in a
layout for adding a forgotten feature when it appears as though there
is not a square micron left. This possibility was mentioned when
discussing buffer insertion on optimization in Chapter 3.
Figure 4.3 shows how an additional feature in the left part of the illustration is undersized to make it fit into the IC layout. Once inserted, it is “inflated” through compaction to satisfy all the IC design layout rules. Features can be inserted that are desired or required, but may have been forgotten during IC layout design. In addition, a process change could dictate the insertion of some feature (e.g. a diode). This kind of flexibility can be very useful.
Fig. 4.3 Insertion of Nonfitting Feature With Compaction
Finally, although compaction will enforce all layout and electrical design rules, it cannot verify the correct topology or guarantee that LVS is correct. These features have to be tested independently of compaction. The IC layout designer has to make sure the layout he has created is not only laid out correctly but also performs functionally correct.