The focus up to this point has been on digital circuits. What about retargeting analog or mixed signal designs? Although digital designs are currently dominant for very many applications, digital circuits need to work together with some analog circuits on the same chip. Can Hard IP retargeting address these kinds of design requirements?

Another interesting challenge in Hard IP retargeting is hierarchy maintenance in the physical layout. For much of the Hard IP migration currently done, the hierarchy of the source layout gets lost during the retargeting process. What about the possibility of maintaining the source layout hierarchy during Hard IP migration?

An extremely efficient method for increasing design productivity would be to reuse designs processed in an outdated technology and to integrate several designs on one chip as an S-o-C in state-of-the-art technology. These designs could be just Hard IP, just Soft IP or - most challenging - Hard and Soft IP mixed and matched. Although a very promising S-o-C scenario, this approach should present some interesting challenges. We will examine some of these challenges.

Guidelines for “good design” have evolved over many years. Comprehensive guidelines for facilitating Soft IP reuse have just recently been presented in the RMM [1].
Because Hard IP reuse and Hard IP-based optimization have been an important aspect of DSM VLSI chip design for a relatively short time, the available data on designs to facilitate working with Hard IP is somewhat limited, still in flux and changing with the evolution of compaction technology. We will discuss what we know now about how to facilitate Hard IP reuse.


In the discussions to follow, we limit the scope to one of the more common fundamental challenges in VLSI chip design and IP reuse: placing analog and digital circuits on the same chip and changing the technology in the process.

Let us assume that we are in a basically digital world, but we need some analog capability on a chip that is mostly digital, a typical mixed signal scenario. Analog capability is often needed in conjunction with digital functions. However, we must exclude high-precision analog circuits from a discussion about migrating analog circuits. High precision in analog circuits may mean microvolt-level balancing between certain devices. Such circuits are difficult enough to design and produce as standalone chips and are manufactured in processes specially designed for analog ICs. Such circuits can not and should not be “mixed and matched” with digital circuits on the same chip.

If the analog circuit we are about to migrate is a necessary part of the original, mostly digital chip that now needs to be retargeted, it has already been designed to “live” with the digital functions on the same chip. Most likely, this case will be manageable. If the analog circuit is a standalone IC, finding itself together with digital functions in a S-o-C scenario may present serious technical difficulties.

Long before physical layout became so critical for digital designs, layout was of paramount importance for VLSI analog designs. While today's digital VLSI circuits consist almost entirely of transistors alone, analog functions require circuits to contain “all” the electrical elements: transistors, resistors, capacitors and inductors. However, because it is difficult to make inductors and sizable capacitors in VLSI circuits, design techniques evolved to generally do without inductors and to live with small capacitance values.

Instead of getting into a full-blown discussion on analog VLSI circuit design, let us review some of the key layout-related parameters for analog circuit performance and then examine how they may be addressed in a VLSI circuit environment and, in particular, for retargeting. We will not talk about the effects of interconnects for now.


Some of the more critical physical layout considerations for analog VLSI circuits are:

  1. Because analog circuits need to produce a continuum of DC and AC signal levels accurately, and not just binary ones and zeros, the values of the electrical elements need to be accurate. However, while it is difficult to control absolute resistance and junction capacitance values in IC technology, the relationship, or ratio, between similar value resistances and similar value capacitances can be controlled easily. Well designed analog circuits work based on ratios rather than absolute values. Some of the most popular components in analog circuits are differential amplifiers because their performance is closely related to ratios and relationships between pairs of components of equal size or value. We need to examine how to retarget without disturbing these ratios.
  2. Symmetry and its maintenance are also very critical. Thus, we must examine how migration might affect symmetries or can be performed to maintain them. This is also particularly critical for transistor pairs.
  3. When measuring the performance of analog circuits, speed is generally measured as a frequency response that consists of amplitude and phase components. The behavior of many analog circuits is particularly sensitive to the phase component. Thus RC time constants are very critical. Again, it is the ratios between time constants that are the most critical.
  4. The DC-related parameters of transistor and resistor pairs need to match. However, even if pairs of transistors, capacitors, resistors are well matched, the orientation in the layout needs to be such that the matching pairs are on equithermal and equipotential lines in the chip. Matching pairs mean nothing if they are at different temperatures or if externally generated voltage differences cause different biases in the circuit. We should mention here that a mere 26 millivolts forward bias across a junction double the current in that device. When signal- and power-generating digital circuits are placed in the neighborhood of analog circuitry, deleterious voltage and temperature gradients may occur.

The need to satisfy the above conditions suggests that there are two scenarios that look promising for successful retargeting of analog blocks:

  1. A chip that contains digital and analog is migrated to a different process. Obviously, analog and digital worked together successfully in a previous process on such a chip. Thus, the layout considerations just discussed were either satisfied or some of them did not apply. “Intelligent” compaction should be all that is required to get these chips to work.
  2. As in an S-o-C scenario, blocks from more than one chip are migrated onto one. Obviously, this is a much more challenging situation. The manufacturing processes for these circuits may have been different. The orientation and the location of the migrated blocks on the new chip are crucial for the analog part. Thus, not only the intelligent compaction but intelligent floorplanning will be required.

When migrating analog circuits, one of the most fundamental requirements is to be able to “recognize” the function of devices on a chip. The compactor needs to recognize transistors, capacitors and resistors amidst the sea of polygons in the layout database. If we can recognize these components in the layout, we can specify what should happen to them during migration.

Having stated all these constraints, can analog be successfully migrated?

The answer is actually yes, irrespective of the above conceptual statements, because it has been done by several users of migration tools.

Let's review how reasonable it is to consider analog migration.