To create a new layout, we need a layout editor. There are several on the market. Using a layout editor is most productive if the designer using it does not have to worry about layout rules. A combination of a compactor and a layout editor provides this type of solution. As with DREAM, all the design rules are in the database of the compactor. In fact, a compaction engine just like the one used for DREAM can be integrated into a layout editor and voila! The problem is solved.

Sagantec offers just such a product called “Companion” because it is a companion to the layout editor. Enormous productivity improvements can be achieved using such a combination of tools. We have discussed the basic ideas about Companion in Chapter 4. In Figure 6.2, we show a commercial version of Companion seamlessly integrated into the Cadence Virtuoso Layout Editor environment.

Fig. 6.2 Sagantec's Companion in Cadence's Virtuoso Environment

At present, there are not any commercial products to optimize layout geometries by varying the drivers (transistors) and the load (interconnect) simultaneously, in order to find the optimal sizing of their combination, but there are products at the university level as mentioned [3]. As we have suggested in Chapter 4, transistors and interconnects must be optimized simultaneously for the ultimate layout optimization. However, there are intermediate commercial solutions and we will have a look at them now. We will discuss a product that allows optimization of transistor sizes without addressing the interconnects and we will discuss a product that allows certain manipulations on interconnects without addressing the transistor sizing. First, transistor sizing. There is a commercial product for finding the best combination of sizing of transistors. The product, called AMPS, is available from Synopsys. AMPS determines the best transistor sizes to optimize a VLSI chip layout for power, speed and area simultaneously. For interconnects, another commercial product called XTREME helps improve VLSI chip performance by manipulating the physical characteristics of interconnects. This product is available from Sagantec.

We will discuss some of the details of these tools below and examine where that leaves us in terms of performance optimization of DSM VLSI chips.

A traditional approach to obtaining the desired performance in a VLSI chip is based on changing transistors sizes by exchanging them for larger or smaller devices to obtain stronger or weaker buffers. This is a rather established technique that was clearly the way to go before DSM technologies. This approach worked well for synthesis or even custom designs, especially in view of the lack of more sophisticated layout optimization algorithms. It is a generally established pattern in performance optimization. Designers feel comfortable with this approach. Based on this established way of thinking, we would expect to see a similar initial thrust in physical layout optimization tools even for DSM technologies. This is indeed the case. The only commercially available too) for optimizing physical layout focuses on transistor geometries. This tool, called AMPS, is available from Synopsys.

Of course, there is a significant difference between the traditional attempts to find the best transistor drive strengths and AMPS. While a tedious and time-consuming trial-and-error approach was traditionally used in order to (hopefully) find the best transistor sizes, AMPS uses the power of the computer and optimization algorithms to do the work for us. AMPS can simultaneously optimize following user-specified design requirements for delay, power, timing slack or power/delay/area cost functions for digital CMOS designs. In conjunction with another Synopsys product called ACE, AMPS can also serve to optimize analog circuits.

Since AMPS is an analysis tool, it only analyzes the transistor sizes. AMPS does not change the physical layout but rather modifies the schematic. Changes in the circuit can then occur by means of resynthesis in a prelayout mode or modification in the physical layout in a postlayout mode. We have already discussed the two options of going through a resynthesis flow versus simply changing the transistor sizes with compaction.
For prelayout, resynthesis-type replacement of transistors, interconnect effects are estimated, and there needs to be enough room available for placement of different sized transistors. This approach literally requires leaving empty room around transistors in anticipation of timing difficulties. This is really difficult to plan for. If there is not enough space, rerouting may be required, which could seriously change the timing of the chip. This may generate a significant amount of work and, in fact, it may force the designer into a rework cycle to achieve timing closure.

On the other hand, with compaction, postlayout adjustment of the transistor sizes is very easy. It is also much more accurate, since values for the parasitics of interconnects are based on parasitics extracted from the layout. Of course, space is also needed with compaction. However, with compaction, space can be created, as we discussed in Chapter 3 and demonstrated in Figure 3.1. Space can be created through the compaction process because layout features other than the transistors are allowed to change to make things fit. Polygons can be moved wherever there is some space as long as no process layout rules are violated. That does not mean that the transistor enlargements suggested by AMPS can always be accommodated. But it does mean that the chances are much greater than they are when just trying to exchange any of the transistors with larger ones. Thus, the combination of AMPS with a compaction engine such as DREAM is very appropriate and powerful.

AMPS requires the input from a timing analyzer and a power analyzer such a Pathmill or PowerMill from Synopsys in order to determine the required transistor modifications for either timing or power optimization.

In conjunction with compaction tools, AMPS also addresses the issue of hierarchy. When seeking the critical timing or power information, it can proceed on a block-by-block basis or it can ignore the functional boundaries between various blocks on a chip. This is like flattening the design. The pros and cons are similar to what one experiences with other tools. There is a trade-off between finding the best possible total design parameters for a flattened design versus a less optimal solution but simplifying a task and investing less in computational efforts.

Finally, AMPS working with compaction can respect keep-out areas defined in an existing layout or layout to be migrated in order not to disturb established critical timing such as in an analog block or for timing critical clock lines.