Design flows give an intuitive picture of the steps involved in designing a VLSI chip. There are questions about how many steps are required, what kind of tasks have to be performed at each one of the steps, and what skill levels are required. There are questions about the sophistication and cost of required tools. There are questions about the level of control over the outcome, the time required and so on. Just as there are many possible design methodologies, there are just as many possible design flows. The best we can hope for is to choose design flows here that help demonstrate the major challenges with respect to IP reuse.

The main motivation for discussing design and reuse flows here is to attempt to show other angles justifying IP reuse. So far, our discussion has been primarily from a somewhat technical perspective. We also want to see whether IP reuse makes economic and business sense. Do these approaches really yield major productivity improvements? Do we really get a shorter time-to-market? So the main focus here is a comparison between some of the major design flows in general terms. We will limit ourselves to three areas, because they are the major focus of this book.

They are:

  1. A generic design flow using synthesis for pre-DSM chips for which delays caused by interconnects could be ignored.
  2. A generic design flow using synthesis for DSM chips for which delays caused by interconnects significantly affect the performance of the chip.
  3. A Hard IP reuse flow for retargeting any type of physical layout, pre-DSM or DSM, to a new process.

Comparing design flows between pre-DSM and DSM technologies, will give us an idea how many steps are required in order to design a chip in either of the technologies.

Comparing design from scratch with Soft IP reuse and Hard IP reuse will show us how many of the steps in pre-DSM and DSM design flows can be skipped because the information is already available and proven, and how many uncertainties and risk factors can be minimized. Keeping in mind the need for improvements in design productivity, we will look at the steps involved in designing today's complex DSM VLSI chips versus IP reuse methodologies.

The need for a substantial increase in design productivity is what triggered reuse of already existing and previously used designs and retargeting of them to the latest, most advanced processes. Of course, the only part that would literally be reused would be the design content, which is in fact the reuse of the IP content. While additional improvements in performance could be achieved through layout optimization at the same time we retarget a chip, for now, we will only discuss simple retargeting by taking advantage of the tighter, higher performance process layout rules. This will allow us to focus primarily on profit-related issues of Soft IP and Hard IP reuse as standalone processes.

For Soft IP reuse, existing high-level software descriptions of chips can be targeted to newer processes for Soft IP reuse. So what is reused is much - if not most - of the high-level programming, test scripts, simulation scripts, models and programs controlling the Soft IP.

For Hard IP reuse, the existing layout databases will be transformed to represent the new physical layout design rules. Existing simulation and test vector suites and any control program that was developed for the part in question will be reused. In addition, any parts that were developed to satisfy some established standards or that had to pass some elaborate incoming inspection (anybody who has tried to sell chips to some French company knows what I mean) will much more easily be accepted after "just" retargeting.

The refabricated designs will then have higher performance, be denser and thus smaller than in the original layout. Also, several of these retargeted designs, can now be combined onto one chip in an S-o-C approach, yielding much higher levels of integration than previously possible. This retargeting of proven designs to newer technologies has become one of the more promising approaches for achieving the needed productivity gains.

It seems obvious that such reuse of existing, proven designs through retargeting to more advanced technologies, as opposed to starting from scratch, should result in substantial savings in engineering, and reduced risks, while still taking full advantage of the progress in processing technologies. This should also address the hottest issue at present in the market: shortening time-to-market. The main goals are to benefit from the rapid advances in processing technology without paying the heavy price of constantly having to redo a design by reusing the knowledge previously invested in these chips.


In order to go from the concept of a VLSI chip we want to design to the fully tested final chip, we will have lo come up with some "typical" design flow. Of course, what may seem typical lo us may not seem typical to others. We also do not want to make the design flow too complicated, since a rather straightforward flow should do the job when it comes to comparing "the three ways" of getting a chip: design from scratch, Soft IP reuse and Hard IP reuse.

An entire book can be devoted to design methodologies and design flows. An excellent, very recent book from 1998 [2J does just that. Wc will focus here on just the bare minimum.

It is not very difficult to predict the number of steps going through a design flow once. However, it is often extremely difficult to predict how many iterations certain steps in the flow will require to finally get a chip that meets all the desired specifications. But this is exactly one of difficulties with today's DSM VLSI chip designs. It is a problem in terms of such issues as time-to-market, budgeting, engineering resources, tools required and planning for processing line capacity to get the chip fabricated.

In our attempt to compare the efforts and risks of the three flows considered here, it will be difficult to come up with absolute measures. Absolute measures are too unpredictable considering the many possibilities. We will therefore attempt to come up with some meaningful comparative measures between the three approaches.

Accordingly, below we will attempt to assess ...

There are extensive, detailed literature and project descriptions of the steps required for the design and fabrication of a VLSI chip. Of course, most of the really interesting ones, the latest ones, are not available to the public but are accessible only inside companies. Thus, we are forced to speak in generalities.

There are many different approaches. They depend on the complexity of the design, the projected volume demanded in the market place, and the price one is expected to be able to charge for a chip. Then there are the most important requirements for the chip to meet, such as extremely high performance, extreme miniaturization, extreme reliability, extremely low power consumption, very rough environmental demands, many of which are in conflict with each other. In terms of flow, a chip could be designed with gate arrays, with standard cclls, with programmable logic or, possibly, fully customized. It could be a system-on-chip (S-o-C) solution using a combination of some or all the suggested design approaches. This makes it difficult to talk about one or even a typical design flow.

Whatever we choose, evaluations of the design process will still give us a feel for some of the critical issues and help us understand how IP reuse could speed up the process and save engineering resources. Even if we are off on some of these "guesstimates", we will still get the "big picture".
In any case, it is pretty much the best we can do and, no matter what we say, the situation will have changed tomorrow anyway.

The data from the flows may be sufficient to provide an indication of the Return On Investment (ROI). That would be quite useful. Such an assessment is only meaningful, however, on a company-specific basis. One has to know the specific cost of doing business. This obviously varies from company to company.