In Figure 7.1, we can look at a simplified pre-DSM flow. Immediately, one may ask the legitimate question: Why should we even look at a pre-DSM flow? Almost none of today's chips are fabricated using such a flow.

True, but it does demonstrate the total lack of timing closure problems caused by the strong influence of physical layout on liming. It also shows just how much more involved the design of a DSM chip has become. Besides, we will spend very little time discussing it.

Thus, the main characteristic of such a flow is the lack of repeated timing analysis once the physical layout phase starts. Once synthesis has chosen characterized cells that satisfy the timing requirements, timing analysis is finished. If the timing is off, one resynthesizes. However, once the timing is correct, we do not have to return to it after subsequent design steps.

Fig. 7.1 A Simplified Pre - DSM Design Flow

The major verification activities in the flow are functional and timing verification as shown in the flow. There are many additional verification steps within the flow that are not shown in Fig. 7.1. There is also much more that could be said about the individual steps in this flow. However, the same issues and many additional ones will be part of a modern, DSM flow, and we will discuss them in the section about DSM.

As mentioned above, possibly the most significant fact about this pre-DSM flow is that all the timing information is in the active parts of the chip, the design can be handed over to processing, a foundry or other chip maker, based on a functional and timing verified netlist.


In Figure 7.2, we saw a simplified DSM flow. It shows many more steps than a pre-DSM flow, but still only the essential steps.

The flow diagram for DSM shows a lot more timing analysis than it does for pre-DSM. Also, what is not really indicated is that all the timing analysis is based on estimates for the dominant timing element, the interconnects. We do not really know what to use for interconnects until after parasitic extraction. Note that in Figure 7.2, IPO means In Place Optimization.

The flow diagrams should contain the key ingredients for a fair evaluation of the time and efforts necessary to successfully design a DSM chip. Of course, such design flows are "moving targets" in today's fast moving hi-tech world. Ideas for new tools are constantly emerging and, with the increasing complexity, whatever new tools emerge will probably arrive not a moment too soon. Yet, however tentative a flow may be, we need to establish a basis from which we can discuss the major differences between the three flows discussed here.

Fig. 7.2 A Simplified DSM Design Flow