Soft IP reuse has been discussed extensively in the RMM [1], Clearly, savings in time and engineering resources can be obtained with Soft IP reuse. One of the questions for Soft IP reuse is what exactly in an existing design available as code can be reused.
In principle, there is data from an architectural level synthesis (HDL, flow diagram, ...), logic-level synthesis (state transition diagrams, schematics, etc.), geometrical/physical level synthesis (floorplans, routing, layout). Thus, depending on the type of data for the reuse, we have more or less freedom of implementation.

For a behavioral description of the design intent, we are still totally independent of the implementation; for a structural description, we are already bound by the interconnections of components such as gates; and, finally, for a physical description, we have given up a lot of freedom. So, whether we talk of Soft IP or Hard IP, the more definitively the data we reuse specifies a "new" design, the less freedom we will have but the less design time we will spend and the more certainty we will have that the reused part will actually work as expected. So, Soft or Hard IP, there is "no such thing as a free lunch". Some of what we gain in productivity and time-to-market, we lose in degrees of freedom for the design. This is a fundamental rule of life for any reuse.

Thus, if we look at Figure 7.2, the early steps, such as specification and coding, clearly do not have to be repeated. We may be able to reuse the simulation and test vector suite for some designs. Just exactly where the total reuse approach breaks down is difficult to generalize. Of course, one should reuse as much as possible.

As for the chances of designing correct silicon the first time, some say that the disconnect between the front-end logical database from the back-end physical database is almost complete. The design industry is making great efforts to close this gap. However, it is difficult to know (and even more difficult to write about) the latest developments that might happen inside the chip design and the design too) industries.

A better connection between front-end and back-end is a must in order to achieve convergence between prelayout and postlayout timing (timing closure). This communication of changes in the netlist during synthesis to back-end tools in order to affect incremental placement and routing is generally called Engineering Change Order (ECO). The good news is that, for any level synthesis, the active parts of a circuit can be accurately characterized a priori. The bad news is that, even for an "ancient" process such as 0.35 microns, interconnects make up for 70% of the delay in a circuit. New formats have been introduced by leading EDA vendors to contain more physical data earlier in the design process. These formats help both Soft and Hard IP reuse.

Some of the formats that are used and are becoming the standard in some cases are:

• LEF Library Export Format
• LLEF Logic Library Expott Format (an extension from LEF)
• DEF Design Export JFortnat (netlist format from Cadence in ASCII format)
• SDF Standard Belay Format (an OVI standard)
• PLEF Physical Library Exchange Format (extension .frofii LEF)
• PDEff Physical Data Exchange Format (an OVI standard)
• SPF Standard Parasitic Format

These formats help, and will be refined with time. However, we have to keep in mind that while PDEF adds to synthesis visibility of physical locations of cells 011 a die to calculate delays for each cluster, it does not have information on routing resources, congestion or die size. SDF communicates delay information between floorplanning and synthesis. Estimated or extracted net capacitance and resistance information is communicated to synthesis via SPF. Also, synthesis-specific scripts. The floorplanning environment can interact with back-end place and route tools using DEF.

Thus, communication formats are gradually put in place to interconnect the front-end with the back-end. However, until a physical layout is complete, all the values are really guesstimates, to put it kindly. Accumulating experience from previously designed chips will help a lot. The rest can be done with posdayout optimization using compaction.

We have seen the short and simple flow for Hard IP reuse. It only suggests some of the applications of the Hard IP compaction methodology. And even the three areas of application...

1. starting with a design existing as layout of a chip or part of a chip that has already been fabricated and in use generally referred to as Hard IP reuse or retargeting,
2. starting with a design that has been laid out after having been designed by whatever means, fully customized, synthesis or any other approach to be optimized with respect to performance, power, density, signal integrity and
3. the stage in a design where we are ready to do the layout or modify and existing layout "by hand" using compaction with its layout design rule database,

may represent only part of where postlayout modifications will become necessary as minimum chip layout dimensions continue to shrink. Of course, this is speculative but certainly a possibility.

For comparing the various flows. will focus primarily on Hard IP retargeting.

As we have seen, it is difficult to exactly quantify the advantages of one method over others. There are too many variables, and now we are going to add some more. However, we do have some ideas about the competing factors for any particular project, for a given company organization and the available resources in terms of tools, engineering staff, infrastructure, etc.

Thus far, we have not talked about the cost of the tools needed to do the job: software and hardware. We have only seen that to verify the correct behavior of a chip alone we may need simulators of various levels and flavors such as cycle-based, event-driven, worst case. We may need to use formal verification. We may need to use emulation. We certainly need to use timing analysis tools. We have not looked at the cost of all the synthesis-related tools, the routers, the floorplanners. Anyway, there is no point to developing a detailed catalog of what is needed here. All these tools and more are needed for Soft IP reuse.

For Hard IP reuse, we need timing analysis and the migration software and quite some computer power to do the migrations.

For both Soft IP and Hard IP reuse, we need layout verification tools.

Then there is the question of the skills required. For Soft IP reuse, engineers primarily need to have computer science backgrounds with a proclivity for architectural creativity. This is what everybody learns in school today. For Hard IP reuse, the skills are more related to semiconductor physics and processing with a penchant for details. This is what used to be popular in university curricula.

The question is how to organize a company to do both areas well. At this point, Hard IP migration is not easy enough that it can be done "once in while" by whoever has nothing else to do. It takes dedication.

Finally, just how much useful, hard-to-sacrifice Hard IP is there just floating around in a company? Probably a lot in some companies. Can management convince engineers to reuse this Hard IP as opposed to do what they like most, design a new chip no matter how long it takes or what is costs?

To conclude, very objective decisions are needed, many on the managerial level. On the other hand, Hard IP retargeting still has to get easier to use and needs to be integrated into overall Soft IP/Hard IP reuse flows in such a way that, in a S-o-C approach, for instance, the mixing and matching becomes natural. In many projects, there are some major blocks for which there are simply no reasons to redesign as opposed to reuse with Hard and Soft IP.

During 1999 and 2000, it has become very evident that the advanced semiconductor manufacturers and design houses are increasingly introducing IP reuse flows, both Soft and Hard IP.
The complexity of the chips which are designed and will be designed, combined with the required resources to do so and the critical time-to-market windows which are faced, simply does not offer any other alternative but to seriously consider at least a partial IP reuse strategy. In addition, we are seeing fast progress in new process technologies which will further stimulate strong growth in the Hard IP flow. There are some significant developments in the area of resynthesis, as well, with newly developed design flows which create "correct timing" layout directly from the netlist level, but these developments are too premature to be considered seriously at this stage.
Also these developments are mainly geared towards cell-based designs and subsequently do nothing for the large fully custom designs.

IP reuse therefore is bound to increase and there are substantive estimates which estimate the total IP reuse market worldwide to reach the level of over 2 billion dollars in 2001, 75% of which is Hard IP reuse. This is a significant development which will finally draw the attention of the chip design industry to the back-end or layout.
At the end of the day, all that matters is if a company is able to produce and deliver the right products at the right time. Only then will it do well.