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|
| 3 |
HARD IP OPTIMIZATION |
| 3.1 |
What to Optimize in a Layout and How |
| 3.2 |
Leverage of Layout on Performance |
| 3.2.1 |
The Increasing Influence of Layout on Performance |
| 3.2.2 |
Optimization Requires a Detailed Layout Analysis |
| 3.2.3 |
Front-end Leverage |
| 3.2.4 |
Back-end Leverage |
| 3.2.5 |
Features Compaction Changes, Features It Does Not |
| 3.2.6 |
Synergy Between Front-end and Back-end? |
| 3.3 |
The Modeling of Interconnects |
| 3.3.1 |
Parasitic Components of the Interconnects |
| 3.3.2 |
Determining Values for the Parasitics |
| 3.3.3 |
Capacitances Affecting Interconnects |
| 3.4 |
Time Delay Analysis in Digital VLSI Circuits |
| 3.4.1 |
Modeling for Timing Analysis |
| 3.5 |
Performance Optimization with Layout Parameters |
| 3.5.1 |
Front-end Optimization |
| 3.5.2 |
Back-end Optimization |
| 3.6 |
Capacitive Effects Between Interconnects |
| 3.6.1 |
Cross-Coupling Between Interconnects |
| 3.6.2 |
Minimizing Cross-Coupling |
| 3.7 |
Optimizing the Active Part |
| 3.7.1 |
Other Optimization Issues |
| 3.8 |
Conclusions to Performance Optimization |
| 3.9 |
Layout Geometry Tradeoffs for Better Yield |
| 3.9.1 |
Yield Enhancement Through Preferred Process Rules, Using
Compaction |
| 3.9.2 |
Yield Enhancement Through Minimizing Critical Areas, Using
Compaction |