A year ago I wrote about the emerging "verification crisis" caused by the dramatically increasing difficulty of functional verification of complex ICs. This crisis is no longer emerging; we are living with it today and it continues to grow in severity. In fact, the 2001 International Technology Roadmap for Semiconductors states, "Without major breakthroughs, verification will be a non-scalable, show-stopping barrier to further progress in the semiconductor industry." Fortunately, creative new approaches to verification are emerging that promise to break through the barrier and to allow the show to go on.
One of the most promising trends is that of property checking and the use of properties as a standard representation of design intent. As this third edition of the Verification Methodology Manual goes to print, Accellera is voting on an industry-standard property language. With the establishment of this open standard, IP vendors, SOC developers and EDA companies will for the first time have a common language for describing desired design behavior independently from design implementation. This language will enable a new generation of formal, semi-formal and dynamic verification tools to emerge that leverage a unified description of design intent and dramatically raise verification productivity. It will also enable the emergence of a "property economy", where property libraries become another component of verification IP that promote verification reuse and speed the verification of cores when integrated in systems.
This edition of the Verification Methodology Manual includes a section on dynamic property checking, a new technique that enables properties to be verified in simulation at any level of design integration. Dynamic property checking complements code coverage in helping determine the completeness of a design's verification. It also complements formal property checking by providing a measurable degree of confidence for properties that cannot be checked formally. This book does contain some references to TransEDA products, but is meant as a general reference to design and verification engineers everywhere. I hope you find it informative and useful.
Chief Executive Officer, TransEDA
Los Gatos, California April 15, 2002
About the authors
David Dempster has worked in the CAE and EDA industry for over 18-years in an applications engineering and training role. He worked for a number of years with Valid Logic Systems and Cadence Design Systems developing and presenting end-user technical training programmes before starting his own design consultancy and management training company. David's work as a management-training consultant has taken him to the four corners of the globe supporting most of the leading-edge electronic and computing companies. David has travelled extensively in the USA, Japan, Korea, Taiwan, Europe and Scandinavia presenting technical workshops on coverage analysis methodology and design tools. During the last two years he has worked very closely with TransEDA developing their customer education training programmes and supporting their exhibitions and road-shows.
Michael Stuart is the Director of Customer and Technical Support at TransEDA. He is a founder member of TransEDA and has held a number of Product Marketing and Customer Support positions at TransEDA including Product Manager for the VeriSure coverage analysis tool. Before joining TransEDA Michael worked as a development Engineer for Veda Design Automation and Siemens (formerly Plessey). Michael holds a first class honours degree in Electronic and Electrical Engineering from Robert Gordon's Institute of Technology, Aberdeen.
It is very tempting to feel that you have to thank everyone that you have ever met in your whole life when compiling the mandatory acknowledgements page. So apart from our chauffeurs, personal hairstylists and house designers, may we single out the following people and pieces of technology for a special mention.
First of all may we convey our thanks to the sales and marketing team at TransEDA who had the original concept for the creation of the Verification Methodology Manual and for keeping us focused and on-track during the compilation phase of the manuscript.
We are also indebted to the senior managers, programmers and technical support personnel at TransEDA for allowing us free use of their coverage analysis tools and workstations, and for giving us unlimited access to their technology, in-depth documentation and research papers. May we also thank Chris Rose at Saros Technology for providing us with a copy of ModelSim 5.5 from Model Technology (now owned by Mentor Graphics) that enabled us to simulate all the worked examples that are referenced in this manual.
We would also like to thank Thomas Borgstrom (Vice President, Marketing at TransEDA) and Jeffrey Barkley (Marketing Manager at TransEDA) for their valuable contribution to the two chapters entitled - FSM Coverage and Dynamic Property Checking.
Thanks must also go to Chris Moses, of TransEDA, for his graphical expertise and hard work turning our rough sketches into drawings that illustrated so clearly the information we wanted to convey.
We would also like to acknowledge the contribution that the Internet made to our work by enabling us both to stay in communication with each other and to provide the review team with regular `copy' while we held down full-time jobs which involved a considerable amount of travel visiting customers worldwide.
Michael would like to thank his wife, Sheila for her support, encouragement and typing skills.
Finally we would like to thank Adobe Inc. for producing FrameMaker, the excellent desktop publishing and document management package that enabled us to seamlessly create a book out of a series of individual chapters, authors' rough notes and random thoughts.
David Dempster and Michael Stuart
This manual has been specifically designed to help and support:… Experienced circuit designers who use the Verilog or VHDL hardware description languages, and are interested in increasing the productivity and quality of their work.
… Engineering managers or project leaders who are seriously considering the benefits and implications of incorporating coverage analysis tools in the design flow.
… Verification and test engineers who are responsible for proving that a design completely meets its specification prior to sign-off.
… Engineers involved in evaluating EDA design tools who require an in-depth understanding of how these tools operate and the benefits that can be achieved.
Although Chapter 3 covers a brief introduction to coverage analysis concepts, as applied to software programming languages, it is assumed that the reader will be familiar with the basic operation of the Verilog or VHDL hardware design languages.
If you are unfamiliar with coverage analysis tools then you should read carefully through each chapter and try out the worked examples in Appendices B to G. This approach should enable you to build up a good understanding of the concepts of coverage analysis as applied to the Verilog and VHDL hardware description languages. It will also provide you with an opportunity to acquire some first-hand practical experience in the use of these tools.
Experienced designers and verification engineers will probably find Chapters 6 thru 12 a useful starting point. These chapters cover the practicalities of applying coverage analysis measurements to HDL source code; how to interpret the results obtained with these tools, and how to manage/optimize the test suite.
If you are an engineering manager or project leader you could start by reading Chapters 4, 5 and 7. This will enable you to find out how coverage analysis tools can be used in the design flow and appreciate some of the benefits that can be achieved with these tools. Chapters 6, 9, 10 and 12 should then be studied in order to understand the practicalities of applying a coverage analysis tool to a project.
If you are planning to carry out an evaluation of a coverage analysis tool you will find that Appendices A to G contains some useful reference material and access to a number of on-line resources.