Flypages and Copyright conditions Contents Foreword ix About the authors x Acknowledgements xi Preface xii Chapter 1. Overview of Front-End Tools Circuit Design Can Be A Risky Business 1 The Front to Back Design Route 2 Handling Design Changes 5 Summary 6 Chapter 2. Code and Rule Checking in the Design Flow HDL Capture Tools 7 Text Editors 8 Linters 8 Graphical Editors 9 Rule-based Checkers 10 Rule Checking and the Design Hierarchy 13 Chapter 3. Introduction to Coverage Analysis The Origins of Coverage Analysis 17 Applying Coverage Analysis Techniques to HDL 18 Modern Hardware Design Tools 19 Typical Capabilities of Coverage Analysis Tools 20 How Coverage Analysis Tools Operate 20 Analyzing the HDL source code 21 Collecting coverage data from the simulation 21 Presenting the results to the user 22 Command Line and Batch Mode 22 Chapter 4. Coverage Analysis in the Design Flow Current ASIC Design flow 23 Coverage Analysis in the Design Flow 26 IP in the Design Flow 29 Chapter 5. Practical Value of Coverage Analysis HDL Verification Problem 33 Coverage Analysis and HDL Verification 34 Project Management With Coverage Analysis 35 Functional Coverage 36 Regression Testing 36 Gate Level Testing 37 Chapter 6. Coverage Analysis Measurements Structural and Functional Testing 40 Statement Coverage 40 Branch Coverage 43 How Branch Coverage is Calculated 43 Condition and Expression Coverage 44 Multiple Sub-Condition Coverage 45 Basic Sub-Condition Coverage 46 Directed or Focused Expression Coverage (FEC) 46 Path Coverage 49 Toggle Coverage 52 Triggering Coverage 53 Signal Tracing Coverage 54 Dealing with Information Overload 56 Excluding Code 59 Post-Simulation Results Filtering 60 Summary 64 Chapter 7. Coverage Directed Verification Methodology Coverage Analysis in the Design Flow 65 Coverage Analysis at Behavioral Level 65 Coverage Analysis at RTL 66 Coverage Analysis and Transient Behavior 68 Coverage Analysis at Gate Level 69 Coverage Analysis and State Machines 70 Practical Guide Lines for Coverage Analysis 72 Coverage Analysis as a Verification Advisor 73 Coverage Measurements and Targets 74 Saving Simulation Time 76 Number of Coverage Analysis Licenses Required 76 Chapter 8. Finte State Machine Coverage FSM Coverage 79 FSM Path Coverage 80 Reachability Based Path Extraction 81 Manual Path Specification 81 TransEDA's FSM Path Approach 82 Focus On Functionality 82 Supercycle 1 83 Supercycle 2 83 Supercycle 3 84 Simplify Complexity 84 A Complex Example 86 Conclusion 89 Cycles Automatically Extracted by VN-Cover 90 Manually Created Paths for Tap Controller 94 Chapter 9. Dynamic Property Checking Structural Testing 95 Visual Checking 96 Self-Checking Test Benches 96 Pattern Matching 97 Properties 97 Verification Flow 98 Dynamic Property Checking in Operation 99 Collecting Simulation Results 100 Typical method of implementation 102 Chapter 10. Verification Architecture for Pre-Silicon Validation Introduction 105 Pre-silicon Validation 107 Concurrency 107 Automated Test Generation 108 Robust, High-quality Verification IP 108 Ease of Use 109 Leveraging Design and Application Knowledge 110 Right Level of Abstraction 110 Debugging 110 Configurability 110 Reusing the Test Environment 110 Machine Cycles Become Less Expensive 111 An Architecture for Pre-silicon Validation 111 Verification components 112 Intelligent Bus Functional Models 112 Intelligent Bus Protocol Monitors 113 Intelligent Test Controller and Data Checker 113 Conclusion 113 Chapter 11. Overview of Test Bench Requirements Basic Test Bench Construction 115 Coverage Directed Test Benches 117 Test Bench for a Single Module or Single Unit 118 Dealing with Multiple Test Benches 119 Improving Your Testing Strategy 120 Writing Test Benches - Functional Verification of HDL Models 120 Chapter 12. Analyzing and Optimizing the Test Suite The Test Suite 121 Regression Testing 123 Merging Test Bench Results 125 Optimizing the Test Benches 125 Identifying Test Benches for ECO 129 Appendix A. On-line Resources and Further ReadingCoverage Analysis Tools 132 Verification Navigator 132 Design Rule Checker 132 Verilog and VHDL Simulators 133 Verilog 133 VHDL 133 ModelSim Simulator 133 Verilog Source Files 134 VHDL Source Files 134 References for Further Reading 134 Reuse Methodology Manual for System-on-a-chip Designs 134 Writing Test benches - Functional Verification of HDL Models 134 HDL Chip Design 134 Appendix B. HDL Checking - Worked Examples Getting Organized 135 Starting the Rule-Based Checker 136 Selecting a Rule Database 137 Selecting the Run Options 138 Running the Rule-Based Checker 139 Viewing the Results 139 Editing the Source Files 142 Appendix C. Verilog Coverage Analysis - Worked Examples Getting Organized 143 Directory and File Structure 144 Command Line Batch File 144 Parameter File (Global and Local) 145 Collecting Coverage Results 146 Viewing Coverage Results 146 Appendix D. VHDL Coverage Analysis - Worked Examples Getting Organized 155 Directory and File Structure 156 Getting The Results 156 Appendix E. FSM Coverage - Worked Examples Directory and File Structure 165 Command Line Batch File 166 Collecting Coverage Results 166 Viewing Coverage Results 167 State Coverage 172 Arc and Path Coverage 172 State Diagram 173 Cycle Information 173 Appendix F. Dynamic Property Checking - Worked Examples Resources 175 Directory and File Structure 175 Command Line Batch File 176 Description of the Design 177 Collecting Coverage Results 177 Viewing Coverage Results 177 Appendix G. Creating Properties - Worked Examples Getting Organized 183 Background 184 Overview 184 Circular Tour 185 Looping on S2 186 Counting the number of loops 186 Matching two lower level sequences 186 Using a Signals file 186 Glossary A glossary of EDA and CAE terms 195 Index An index of topics in this book 201
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