Appendix A

On-Line Resources and Further Reading


This appendix gives details of how you can acquire a set of software tools and related Verilog and VHDL source files that will enable you to work through the practical exercises and case studies that appear in Appendix B thru to G. The step-by-step practical exercises and case studies have been designed to enable you quickly to acquire experience of the various coverage analysis concepts described in this manual. If you are planning to conduct an in-depth evaluation of the coverage analysis tools, then it is suggested that you do this once you have completed the exercises and developed familiarity with the products.

Although it is assumed that you will probably use the Internet to download copies of the coverage analysis tools and simulators, the software can also be obtained by contacting the appropriate vendor and requesting a compact disc.

Some useful web site addresses and newsgroups are listed below.


Model Technology

Saros Technology (UK)

Verilog newsgroup comp.lang.verilog

VHDL newsgroup comp.lang.vhdl

Coverage Analysis Tools

Full-function copies of the following front-end design tools are available from TransEDA's web site for evaluation purposes.

All the tools operate on the most popular range of engineering platforms including: SUN Solaris, HP Unix, Linux and Windows 2000/NT.

Verification Navigator

Verification Navigator is a comprehensive verification environment that contains a set of tools designed to provide:

code coverage analysis (i.e. VN-Cover),
finite state machine (FSM) coverage analysis (i.e. VN-Cover FSM Analyzer),
property checking (i.e. VN-Property DX),
test suite management and analysis (i.e. VN-Optimize).

All the tools are integrated in an easy-to-use graphical user interface that supports Verilog, VHDL and dual-language designs as well as working with the industry's leading simulators.

Design Rule Checker

The name of the design rule checker available from TransEDA is VN-Check. It is supplied with the following five comprehensive and extensible design rule databases which can be used to validate Verilog or VHDL source files.

Best Practices
RMM (Reuse Methodology Manual)
Portability (VHDL to Verilog or Verilog to VHDL)

Verilog and VHDL Simulators

Verification Navigator and State Navigator coverage analysis products have been designed to support the following leading-edge simulators.


Verilog-XL Cadence Design Systems

NC-Verilog Cadence Design Systems

Verilog-VCS Synopsys Inc

ModelSim Model Technology


Leapfrog Cadence Design Systems

VSS Synopsys Inc

ModelSim Model Technology

If you already own one of these simulators all you need to commence your evaluation is the appropriate coverage analysis tool (i.e. Verification Navigator) and the related set of Verilog and/or VHDL source files.

ModelSim Simulator

An evaluation copy of ModelSim Special Edition (SE) that operates on SUN Solaris, HP 700, RS6000, Windows-95, Windows-98, Windows-NT or Windows-2000 platforms can be requested from Model Technology's software download page on their web site at:

Verilog Source Files

The set of Verilog files, in `zip' format, that are used in the case study and worked examples described in Appendix B and C can be obtained from TransEDA's web site:

VHDL Source Files

The set of VHDL files, in `zip' format, that are used in the case study and worked examples described in Appendix D can be obtained from TransEDA's web site:

References for Further Reading

Reuse Methodology Manual for System-on-a-chip Designs

Authors: Michael Keating and Pierre Bricaud

Published by Kluwer Academic Publishers

ISBN 0-7923-8558-6

Writing Test benches - Functional Verification of HDL Models

Author: Janick Bergeron

Published by Kluwer Academic Publishers

ISBN 0-7923-7766-4

HDL Chip Design

Author: Douglas J. Smith

Published by Doone Publications

ISBN 0-9651934-3-8

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