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Appendix A
On-Line Resources and Further Reading
This appendix gives details of how you can acquire a set of software tools and related Verilog and VHDL source files that will enable you to work through the practical exercises and case studies that appear in Appendix B thru to G. The step-by-step practical exercises and case studies have been designed to enable you quickly to acquire experience of the various coverage analysis concepts described in this manual. If you are planning to conduct an in-depth evaluation of the coverage analysis tools, then it is suggested that you do this once you have completed the exercises and developed familiarity with the products.
Although it is assumed that you will probably use the Internet to download copies of the coverage analysis tools and simulators, the software can also be obtained by contacting the appropriate vendor and requesting a compact disc.
Some useful web site addresses and newsgroups are listed below.
Model Technology www.model.com
Saros Technology (UK) www.saros.co.uk
Verilog newsgroup comp.lang.verilog
Coverage Analysis Tools
Full-function copies of the following front-end design tools are available from TransEDA's web site for evaluation purposes.
www.transeda.com/download.html
All the tools operate on the most popular range of engineering platforms including: SUN Solaris, HP Unix, Linux and Windows 2000/NT.
Verification Navigator
Verification Navigator is a comprehensive verification environment that contains a set of tools designed to provide:
All the tools are integrated in an easy-to-use graphical user interface that supports Verilog, VHDL and dual-language designs as well as working with the industry's leading simulators.
Design Rule Checker
The name of the design rule checker available from TransEDA is VN-Check. It is supplied with the following five comprehensive and extensible design rule databases which can be used to validate Verilog or VHDL source files.
Verilog and VHDL Simulators
Verification Navigator and State Navigator coverage analysis products have been designed to support the following leading-edge simulators.
Verilog
Verilog-XL Cadence Design Systems
NC-Verilog Cadence Design Systems
VHDL
Leapfrog Cadence Design Systems
If you already own one of these simulators all you need to commence your evaluation is the appropriate coverage analysis tool (i.e. Verification Navigator) and the related set of Verilog and/or VHDL source files.
ModelSim Simulator
An evaluation copy of ModelSim Special Edition (SE) that operates on SUN Solaris, HP 700, RS6000, Windows-95, Windows-98, Windows-NT or Windows-2000 platforms can be requested from Model Technology's software download page on their web site at: www.model.com/sales/qualify.html
Verilog Source Files
The set of Verilog files, in `zip' format, that are used in the case study and worked examples described in Appendix B and C can be obtained from TransEDA's web site:
VHDL Source Files
The set of VHDL files, in `zip' format, that are used in the case study and worked examples described in Appendix D can be obtained from TransEDA's web site:
References for Further Reading
Reuse Methodology Manual for System-on-a-chip Designs
Authors: Michael Keating and Pierre Bricaud
Published by Kluwer Academic Publishers
Writing Test benches - Functional Verification of HDL Models
Published by Kluwer Academic Publishers
HDL Chip Design
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